Digital PLLs for multi-GHz clock generat

lkj2003

A digital implementation of a PLL has several advantages compared to its
Analog counterpart. These include easy scalability with process shrink, elimination
of the noise susceptible analog control for a voltage controlled oscillator (VCO) and
the inherent noise immunity of digital circuits. Several recent digital PLL (DPLL)
implementations have achieved performance similar to that of analog PLLs. However,
there is an upper bound on the bandwidth of a DPLL and this limits its
capability to track an input signal. The research described in this thesis is focused
on new digital PLL architectures that overcome this bandwidth limitation in linear
as well as in digital PLLs.

fixit

沙发一个

mynameiswtx

非常感谢！

hujiaomianhao

hao dong xi.

penyu1987

谢谢分享！！

fwutsairlin

thanks!