VHDL

杨学硕

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

PACKAGE shift_type IS
SUBTYPE std4 IS STD_LOGIC_VECTOR(3 DOWNTO 0);
END shift_type;

LIBRARY IEEE;
USE WORK.shift_type.ALL;

ENTITY reg2 IS
PORT(din:IN std4;
     clk,load,left_right:IN STD_LOGIC;
     dout: BUFFER std4);
END reg2;
ARCHITECTURE rtl OF reg2 IS
SIGNAL shift_val: std4;
BEGIN
NXTROCESS(load,din,left_right,dout)
      BEGIN
      IF(load='1') THEN
      shift_val<=din;
      ELSIF(left_right='0') THEN
      shift_val(2 DOWNTO 0)<=dout(3 DOWNTO 1);
      shift_val(3)<='0';
      --ELSIF(left_right='1') THEN
      ELSE
      shift_val(3 DOWNTO 1)<=dout(2 DOWNTO 0);
      shift_val(0)<='0';
      END IF;
    END PROCESS;
CURRENTROCESS(clk)
          BEGIN
          IF(clk'EVENT AND clk='1') THEN
          dout<=shift_val;
          END IF;
        END PROCESS;
END rtl;

显示错误为：Error (10482): VHDL error at reg2.vhd(13): object "STD_LOGIC" is used but not declared
求各位大神帮忙