latchup 失效分析（by Ming-Dou Ker 2006）

semico_ljj

Failure analysis and solutions to overcome latchup
failure event of a power controller IC
in bulk CMOS technology

Shih-Hung Chen a,1, Ming-Dou Ker b,*
a ESD and Product Engineering Department, SoC Technology Center, Industrial Technology Research Institute, 195, Sec. 4,
Chung Hsing Road, Chutung, Hsinchu, Taiwan, ROC
b Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, 1001 Ta-Hsueh Road,
Hsinchu 300, Taiwan, ROC

Abstract
Latchup failure which occurred at only one output pin of a power controller IC product is investigated in this work.
The special design requirement of the internal circuits causes the parasitic diode that is inherent between the n-well and
p-substrate to be a triggering source of the latchup occurrence in this IC. The parasitic diode of the internal PMOS was
easily turned on by an anomalous external signal to trigger the neighbor parasitic Silicon Controlled Rectifier (SCR)
path which causes latchup event in the CMOS IC product. Some solutions to overcome this latchup failure have been
also proposed in this paper.

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Conclusion

From the detailed analyses, the latchup failure was
attributed to the potential of n-well pickup in the PMOS
of the internal circuits in CMOS IC. Due to the special
design concern in the PMOS, the parasitic diode
between the n-well and p-substrate was turned on to
induce a substrate current to trigger the neighbor SCR
path, when a negative latchup voltage/current trigger
source is applied to the pad. To solve this latchup occurrence,
the potential of n-well in the PMOS should be
connected to a higher potential. However, the performance
will be slightly degraded when the n-well pickup
is tied to VDD. On the other hand, the trigger current
can be significantly restrained by adding a resistor
between the I/O cell and the output PMOS in internal
circuits. To re-draw the chip layout with a wider spacing
from the PMOS and its neighborhood, as well as a
wider P+ guard ring to surround the PMOS, is suggested
to overcome such latchup failure in this IC
product.

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References

[1] Hargrove MJ, Voldman S, Gauthier R, Brown J, Duncan
K, Craig W. Latchup in CMOS technology. In: Proceedings
of IEEE international reliability physics symposium,
1998. p. 269–78.
[2] Chen JY. CMOS devices and technology for VLSI. Prentice-
Hall International; 1990.
[3] Troutman RR. Latchup in CMOS technology. Kluwer
Academic Publishers; 1986.
[4] Aoki T. A practical high-latchup immunity design methodology
for internal circuits in the standard cell-based
CMOS/BiCMOS LSIs. IEEE Trans Electron Dev 1993;40:
1432–6.
[5] Ker M-D, Lo W-Y, Chen T-Y. Compact layout rule
extraction for latchup prevention in a 0.25-lm shallowtrench-
isolation silicided bulk CMOS process. In: Proceedings
of international quality electronic design, 2001. p.
267–72.
[6] Ker M-D, Lo W-Y. Methodology on extracting compact
layout rules for latchup prevention in deep-submicron bulk
CMOS technology. IEEE Trans Semicond Manufact 2003;
16:319–34.

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