Sr. ASIC Design / DFT ENGINEER

jingli888ca

Contact: jingli888ca@163.com for further information.

RESPONSIBILITIES:
- Create feature improvements, implement and verify memory BIST, Scan, XOR tree, JTAG, analog macros and chip level test controller.
- Micro-Architecture; working closely with chip design teams on defining DFT testing strategy.
- Support multiple projects with DFT feature integration, simulation, debugging, synthesis, timing closure, bring-up, etc.
- Memory BIST, Scan, IO, ATE vector generation, lab bring up and DFT failure analysis.

MINIMUM REQUIREMENTS:
- Looking for ASIC / Logic Design engineers with backgrounds in DFT/Scan/memory testing.
- The candidate will be familiar with DFT test methodology, DFT architecture and DFT related failure analysis, as well as JTAG/1149.1
- The ideal candidate will also be familiar with ASIC/Logic design flow including verilog coding, verification, simulation, timing analysis, ECO, bringup, ATE test development.
- Programming skills in C++, PERL and TCL.
- Ideal candidate must possess good communication skills in both Chinese, English and the ability to work well as a team.
- BS, MS in Electrical Engineering with 3-5 years of experienceu