Application note : RF Design Guidelines-PCB Layout and Circuit Optimization

homerican

RF Design Guidelines-PCB Layout and Circuit Optimization
1 Table of Contents
1 Table of Contents............................................................................................................................2
1.1 Index of Figures .....................................................................................................................2
1.2 Index of Tables ......................................................................................................................2
2 Introduction .....................................................................................................................................3
3 General PCB Layout Techniques ....................................................................................................4
3.1 4-Layer Designs.....................................................................................................................4
3.2 2-Layer Designs.....................................................................................................................5
3.3 PCB Transmission Lines .......................................................................................................6
3.4 Current Loops and Decoupling..............................................................................................7
3.5 PCB Parasitics......................................................................................................................7
4 RF Device PCB Layout and Optimization........................................................................................9
4.1 Thermal Relief Pad ................................................................................................................9
4.2 VCO and Loop Filter ..............................................................................................................9
4.2.1 PCB Layout .......................................................................................................................9
4.2.2 Optimization....................................................................................................................11
4.3 Transmitter Circuit ...............................................................................................................12
4.3.1 Optimization....................................................................................................................12
4.3.2 PCB Layout .....................................................................................................................16
4.4 Receiver LNA Circuit ...........................................................................................................16
4.4.1 PCB Layout .....................................................................................................................16
4.4.2 Circuit Optimization .........................................................................................................17
5 Passive Components .....................................................................................................................20
5.1 Capacitors...........................................................................................................................20
5.2 Inductors ..............................................................................................................................21


1.1 Index of Figures
Figure 1: Semtech Transceiver Architecture...........................................................................................3
Figure 2: 4-Layer PCB Build-Up .............................................................................................................4
Figure 3: 2-Layer Reference Design.......................................................................................................5
Figure 4: PCB Microstrip Trace...............................................................................................................6
Figure 5: Circuit Decoupling and Current Loop Minimization .................................................................7
Figure 6: PCB Via ..................................................................................................................................8
Figure 7: Multiple Via Connection of Thermal Pad .................................................................................9
Figure 8: VCO Tank Circuit Layout .......................................................................................................10
Figure 9: PLL Loop Filter.......................................................................................................................10
Figure 10: Semtech Loop Filter Configurations ....................................................................................11
Figure 11: TX Matching Network ..........................................................................................................12
Figure 12: Measurement of Optimum Load Impedance Presented to the Transmitter ........................13
Figure 13: Design of Pi-Section Filter ...................................................................................................14
Figure 14: Impedance Transformation..................................................................................................15
Figure 15: Optimized Matching Circuit..................................................................................................15
Figure 16: Transmitter Section PCB Layout .........................................................................................16
Figure 17: LNA Matching Network ........................................................................................................16
Figure 18: LNA PCB Layout..................................................................................................................17
Figure 19: Measurement and Optimization of the LNA Matching network ...........................................18
Figure 20: Optimized LNA Matching Network Input Reflection Coefficient ..........................................18
Figure 21: I and Q Channel Output Signals ..........................................................................................19
Figure 22: Equivalent Circuit of a Multilayer Ceramic Capacitor ..........................................................20
Figure 23: Inductor Equivalent Circuit...................................................................................................21


1.2 Index of Tables
Table 1: Optimum Transmitter Load Impedance ..................................................................................13
Table 2: Typical I, Q Signal Amplitudes ................................................................................................19
Table 3: Typical Decoupling Capacitor Values .....................................................................................20
Table 4: Typical Inductor Types............................................................................................................22

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