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我在顶层设计中使用如下代码使用的dcm:
-- exteranl xtal clock input to get the global clock buffer
ibufg1 : IBUFG port map (I => XTAL_CLK, O => CLK);
-- digital clock manager 1
dcm1 : DCM port map (CLK0 => ClkB, CLK2X => ClkA,
LOCKED => Locked1, CLKFB => mclk, CLKIN => Clk, RST => RESET);
--sdr_clk is routed directly from dcm0 to output buffer
obuf1 : OBUF_F_16 port map (I => ClkA, O => sdr_clk_inst);
sdr_clk <= sdr_clk_inst;
--mclk is extimated to be 100MHz
--vgaclk is extimated to be 50MHz
bufg1 : BUFG port map (O => mclk, I => ClkA);
bufg2 : BUFG port map (O => vgaclk, I => ClkB);
----------------------------------------------------------------
-- Generate the reset_n signal
RESET_n <= '0' when RESET = '1' and Locked1 = '0' else
'1';
而且没有做component declaration,能够通过综合,而且看报告的话说用了一个dcm和两个global clock buffer。但是有一些警告:
WARNING:Xst:1537 - d:/hitsxpersonal/xilinxdev/intergralvga/xvga.vhd line 142: Generic <MAXPERCLKIN> of type Time is ignored.
WARNING:Xst:1537 - d:/hitsxpersonal/xilinxdev/intergralvga/xvga.vhd line 142: Generic <MAXPERPSCLK> of type Time is ignored.
WARNING:Xst:1537 - d:/hitsxpersonal/xilinxdev/intergralvga/xvga.vhd line 142: Generic <SIM_CLKIN_CYCLE_JITTER> of type Time is ignored.
WARNING:Xst:1537 - d:/hitsxpersonal/xilinxdev/intergralvga/xvga.vhd line 142: Generic <SIM_CLKIN_PERIOD_JITTER> of type Time is ignored.
WARNING:Xst:1537 - d:/hitsxpersonal/xilinxdev/intergralvga/xvga.vhd line 142: Generic <MAXPERCLKIN> of type Time is ignored.
WARNING:Xst:1537 - d:/hitsxpersonal/xilinxdev/intergralvga/xvga.vhd line 142: Generic <MAXPERPSCLK> of type Time is ignored.
WARNING:Xst:1537 - d:/hitsxpersonal/xilinxdev/intergralvga/xvga.vhd line 142: Generic <SIM_CLKIN_CYCLE_JITTER> of type Time is ignored.
WARNING:Xst:1537 - d:/hitsxpersonal/xilinxdev/intergralvga/xvga.vhd line 142: Generic <SIM_CLKIN_PERIOD_JITTER> of type Time is ignored.
应改怎么消除呢?
我在顶层设计的ucf文件中的dcm部分是这么设定的:
NET "XTAL_CLK" PERIOD = 60MHz HIGH 50 %;
NET "mclk" TNM_NET = "mclk";
TIMESPEC "TS_mclk" = PERIOD "mclk" 110 MHz HIGH 50 %;
NET "vgaclk" TNM_NET = "vgaclk";
TIMESPEC "TS_vgaclk" = PERIOD "vgaclk" 60 MHz HIGH 50 %;
其中xtal_clk是外部晶振输入的时钟,mclk和vgaclk是经过bufg生成的时钟。
想问一下这样设定dcm是否正确? |
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