Cadence is looking for IC design,design services and verification Engineer

kengteng

SOC-R Front-end Design Team

Principal Verification Engineer

Location:Shanghai/Beijing

Positiondescription:

Deliver/implementadvanced verification solutions by utilizing Cadence’s Incisive Verificationproduct portfolio. The engineer should be able to act as a strong team memberand contributor, leading team projects and initiatives. Exercise judgmentwithin generally defined practices and policies.

Specific duties include:

--Deepunderstanding on ASIC/SOC design flow

--Excellent knowledge of advanced verificationmethodology like eRM/OVM/UVM

–Familiar with Cadence’s Incisive Plan toClosure Methodology (IPCM)

--Proficiency in System Verilog,  SystemC and/or e (Specman)

–Developing and using Verification Components(eVC, OVC, UVC, VIP)
–Developing and usingassertion based verification and formal analysis methods

--Skilled in scripting language, such asPerl, C shell, Makefile
–Assessing the project verification requirements
–Operating in a lead roleregarding architecting and implementation of project verificationenvironment/solution.

–May coordinate/lead others within the scopeof a defined project

Essential Qualifications:

-Must have BS degree with 10+ yearsof applicable experience, MS degree with 7+ years of applicable experience inelectrical engineering, microelectronics, comparable engineering science orsolid state physics.

-Essential that the individualdemonstrates strong communication, verbal and written. Requires goodcommunication skills in English.

DesirableQualifications:

A minimum ofseven years relevant experience in industry.

- Will have demonstrated hands-onexperience and expertise with Cadence verification design tools or equivalenttools, flows and methodologies required to execute a verification project.

- Will have demonstrated successfulcompletion of 10+ verification projects as an individual contributor

- Will have ARM based SoC designs atsystem project verification experience

SOC-R Physical Design Team

Position: Lead Physical Design Engineer

Location: Shanghai

Position Description:

-Perform physical design implementation,including synthesis, floor planning, power grid design, place and route, clocktree synthesis, timing closure, power/signal integrity signoff, physicalverification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical designproject management.

-The candidate will have theopportunity to work on many varieties of challenging designs, i.e. low powerand high speed design. The responsibility includes participating in or leadingnext generation physical design, methodology and flow development.

                                                         

Position Requirements:         

1.BS degree with 10+ years ofapplicable experience, MS degree with 7+ years of applicable experience inelectrical engineering, microelectronics.

2.Experienced with ASIC design flow,hierarchical physical design strategies, methodologies and understand deepsub-micron technology issues.

3.Solid knowledge on LP Design, DFT,static timing analysis, EM/IR-Drop/crosstalk analysis, formal verification,physical verification, DFM.

4.Successful track records of tapingout complex, 65/40/28 nm SOC chips.

5.Automation and programming-minded,solid coding experience in Makefile/Tcl/Tk/Perl.

6. Self-motivated, able to workindependently or as a team player, excellent verbal and written communicationskills in English.

If you have interest, PLS send yourCV to zhangyl@cadence.com

SOC-R Design Services Team

Position: Lead Implementation Services Engineer

Location: Shanghai

Position Description:

1.The candidates should be senior ina way that they are not only technical excellent but also mature & able tocommunicate with customers, following team members.

2.This engineer should have excellentdesign experiences in the digital implementation domain including Floorplan,P&R, STA, Physical verification, DFM.

3.The engineer must have a solidbackground in circuits, electronics & physics & should be very willingto learn new stuff.

Key Accountabilities:

1.Ability to handle large sizeddesign implementation tasks & architectural tasks alone. 2.Ability toassess Customer's Design environment, to understand his application needs &to build new Design environment based on specifications & available Cadencetool technology.

3.Ability to acquire a basicunderstanding of the (services) business environment of Cadence within 1 month.

4.Working on multi person projects ofvarying complexity, working especially in a multi-site/multi-cultural project.The latter requires good communication skills in English. 5.Feeling responsiblefor technical delivery as well as business development & opportunitycreation. Behavioral competencies: Teamwork; Customer focus; 6.Accountability; Communication;Coaching & feedback; Employee development; Leadership.

                                                         

Position Requirements:         

1.BS degree with 10+ years ofapplicable experience, MS degree with 7+ years of applicable experience inelectrical engineering, microelectronics.

2.Essential that the individualdemonstrates strong communication, verbal and written, and project managementskills.

3.Requires good communication skillsin English.

If you have interest, PLS send yourCV to zhangyl@cadence.com