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发表于 2012-12-24 15:04:55
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显示全部楼层
module my_test(input clk,input rst,output d0,output d1);
reg a,b;
assign d0 = a;
assign d1 = b;
always @(posedge clk)
begin
if (rst)
a <= 1'b0;
else
a <= ~a;
end
always @(posedge clk)
begin
if (rst)
b <= 1'b0;
else
begin
if (b == 1'b1)
b <= 1'b0;
else
b <= 1'b1;
end
end
endmodule
已经试验没问题。软件平台的不同版本可能有些支持不够,建议用最新的 |
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