这个def文件怎么改成Verilog-A文件？

liufengchun100 · 发表于 2012-12-14 15:49:13

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用spectre仿真时，模型库里有个res.def文件，看名字是电阻模型定义文件，但仿真的时候总是出错，
提示：
   FATAL (VACOMP-2096): File '/home/Cadence/../models/spectre/res.def' does not appear to be a valid Verilog-A file. In previous releases, '.def' was a file extension typically used for SpectreHDL files but SpectreHDL is no longer supported. If this file is a SpectreHDL file, you need to replace it with an equivalent Verilog-A file.

怎样才能转换为Verilog-A格式的文件呢？求各位不吝赐教~~谢谢了

res.def 内容如下：

module polyres_hdl (n2, n1, ctrl2, ctrl1) (wr, lr, vc1, vc2, rtemp, tc1, tc2, etch, tnom, rsh0)
node [V, I] n2, n1, ctrl2, ctrl1;
parameter real lr=0.0;
parameter real wr=0.0;
parameter real rtemp=$temp() - 273.15;
parameter real vc1 = 0;
parameter real vc2 = 0;
parameter real tc1 = 0;
parameter real tc2 = 0;
parameter real etch = 0;
parameter real tnom = 25.0;
parameter real rsh0 = 1;
{
real dt, absv, tcoef, vcoef, r0;
initial
{
}

analog
{ dt = (rtemp - tnom);
      absv = abs(V(ctrl2, ctrl1));
tcoef = 1.0 + dt * (tc1 + dt * tc2);
vcoef = 1.0 + absv * (vc1 + absv * vc2);
r0 = rsh0 * lr / ( wr - 2.0 * etch ) * tcoef * vcoef;
V(n2, n1) <- I(n2, n1) * r0;
}

final
{
}

}
module diffres_hdl (n2, n1, ctrl2, ctrl1) (wr, lr, rtemp, vc1, vc2, tc1, tc2, etch, tnom, rsh0)
node [V, I] n2, n1, ctrl2, ctrl1;
parameter real lr=0.0;
parameter real wr=0.0;
parameter real rtemp=$temp() - 273.15;
parameter real vc1 = 0;
parameter real vc2 = 0;
parameter real tc1 = 0;
parameter real tc2 = 0;
parameter real etch = 0;
parameter real tnom = 25.0;
parameter real rsh0 = 1;
{
real dt, absv, tcoef, vcoef, r0;
initial
{
}

analog
{ dt = (rtemp - tnom);
      absv = V(ctrl2, ctrl1);
tcoef = 1.0 + dt * (tc1 + dt * tc2);
vcoef = 1.0 + absv * (vc1 + absv * vc2);
r0 = rsh0 * lr / ( wr - 2.0 * etch ) * tcoef * vcoef;
V(n2, n1) <- I(n2, n1) * r0;
}

final
{
}

}