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发表于 2007-12-14 10:15:45
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Introduction
The EDA industry has acknowledged that functional verification is causing a bottleneck in the design
process and is inadequately equipped to deliver verification of future designs.
Today, designs can no longer be sufficiently verified by ad-hoc testing and monitoring methodologies. More
and more designs incorporate complex functionalities, employ reusable design components, and fully utilize
the multi-million gate counts offered by chip vendors.
To test these complex systems, too much time is spent constructing tests as design deficiencies are
discovered, requiring test benches to be rewritten or modified, as the previous test bench code did not
address the newly discovered complexity. This process of working through the bugs causes defects in the
test benches themselves. Such difficulties occur because there is no effective way of specifying what is to
be exercised and verified against the intended functionality.
This paper presents a powerful new approach to functional verification that dramatically improves the
efficiency of verifying correct behavior, detecting bugs and fixing bugs throughout the design process. In
this approach, the central focus of the verification process is assertions, which detect bugs, guide the test
writers to write better tests and direct testbenches to produce stimuli. It raises the level of verification from
RTL and signal level to a level where users can develop tests and debug their designs closer to design
specifications. It encompasses and facilitates abstractions such as transactions and properties.
Consequently, design functions are exercised efficiently (with minimum required time) and monitored
effectively by detecting hard-to-find bugs. This methodology is called assertion-based verification, as the
assertions are the primary basis for ensuring that the Design Under Test (DUT) meets the criteria of
design quality. These techniques support two methods: dynamic verification using simulation, and formal
or semi-formal verification using model checking and proof techniques.
Two key technologies are introduced: assertion specifications and functional coverage. Based on these
technologies, a comprehensive functional verification solution is created that incorporates language,
analysis tools and a methodology to produce a next-generation capability. These techniques address
current needs of reducing manpower and time and the anticipated complications of designing and verifying
complex systems in the future. |
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