SystemVerilog Testbench Student Guide & Lab Guide 2011.12（可搜寻 PDF）

lixiayjx · 发表于 2014-11-21 13:50:45

谢谢分享

lixiayjx · 发表于 2014-11-21 13:54:22

文件好大呀

jimcmwang · 发表于 2014-11-24 14:47:21

SystemVerilog Testbench.part1.rar (15 MB)

jimcmwang · 发表于 2014-11-24 14:47:55

SystemVerilog Testbench Student Guide & Lab Guide 2011.12（可搜寻 PDF）
Introduction
The Device Under Test
SystemVerilog Verification Environment
SystemVerilog Testbench Language Basics
Driving and Sampling DUT Signals
Managing Concurrency in SystemVerilog
Object Oriented Programming: Encapsulation
Object Oriented Programming: Randomization
Object Oriented Programming: Inheritance
Inter-Thread Communications
Functional Coverage
SystemVerilog VMM preview

gfangclara · 发表于 2014-11-24 17:46:29

新的設計流程!!

leopard520329 · 发表于 2014-12-2 23:17:24

3ks.lz

tcon1234 · 发表于 2014-12-3 00:05:16

感謝您的分享

tcon1234 · 发表于 2014-12-3 00:06:14

高人佩服啊。

hxdzjk · 发表于 2014-12-3 15:23:48

下载不了呀？？？

神一样的驴子 · 发表于 2015-1-9 12:08:40

楼主好人啊，真好

[资料] SystemVerilog Testbench Student Guide & Lab Guide 2011.12（可搜寻 PDF）

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