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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity jian60 is
port(clk:in std_logic;
start:in std_logic;--倒计时开始
reset:in std_logic;--复位信号
daojishi:in std_logic;--倒计时使能
shishuru,geshuru:in std_logic_vector(3 downto 0);
coutut std_logic;
shi,geut std_logic_vector(3 downto 0));
end;
architecture a of jian60 is
signal i,j:std_logic_vector(3 downto 0);
begin
process(clk,daojishi,start)
begin
if (reset='1') then i<="0000";j<="0000";
elsif (daojishi='1' and start='0') then
i<=shishuru;
j<=geshuru;
elsif rising_edge(clk) then
if start='1' then
if j="0000" then j<="1001";
if i="0000" then cout<='1';i<="0101";
else i<=i-1;cout<='0';
end if;
else j<=j-1;
end if;
end if;
end if;
shi<=i;
ge<=j;
end process;
end;
报错:Only one clock enable signal can be defined for a flipflop |
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