ACTEL的fpga AEP125上电不需要控制上电顺序吗？是不是和atera和xilinx不一样啊？

fgm1982

ACTEL的fpga AEP125上电不需要控制上电顺序吗？是不是和atera和xilinx不一样啊？

fgm1982

自己顶一下，proasic3系列手册上没有明确说上电顺序问题，只说保证满足各个电平的条件，不知道是不是不需要控制上电顺序。

非洲小白脸

一般core最先

fgm1982

The I/O bank VMV pin must be tied to the VCCI pin within the same bank. Therefore, the supplies that
need to be powered up/down during normal operation are VCC and VCCI. These power supplies can be
powered up/down in any sequence during normal operation of IGLOO, IGLOO nano, IGLOO PLUS,
ProASIC3L, ProASIC3, and ProASIC3 nano FPGAs. During power-up, I/Os in each bank will remain
tristated until the last supply (either VCCIBx or VCC) reaches its functional activation voltage. Similarly,
during power-down, I/Os of each bank are tristated once the first supply reaches its brownout
deactivation voltage.

cyzhai

一般core最先

diyangguang

谢谢楼主

mangotango

i need lic

mangotango

great info