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楼主 |
发表于 2012-9-26 11:43:19
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The I/O bank VMV pin must be tied to the VCCI pin within the same bank. Therefore, the supplies that
need to be powered up/down during normal operation are VCC and VCCI. These power supplies can be
powered up/down in any sequence during normal operation of IGLOO, IGLOO nano, IGLOO PLUS,
ProASIC3L, ProASIC3, and ProASIC3 nano FPGAs. During power-up, I/Os in each bank will remain
tristated until the last supply (either VCCIBx or VCC) reaches its functional activation voltage. Similarly,
during power-down, I/Os of each bank are tristated once the first supply reaches its brownout
deactivation voltage. |
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发表于 2012-9-24 18:06:24
