NVIDIA上海急招ASIC Physical Design Engineer

NvidiaHR

NVIDIA Shanghai is now looking for ASIC PHYSICAL DESIGN ENGINEER, if you are intereted in it, pls feel free to contact me(Sarah Su).
Email: sasu@nvidia.com
MSN: suwei198702@hotmail.com
QQ: 524786472
Pls refer to the JD as below:
As a member of our global ASIC-PD team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology), partition/full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic
RESPONSIBILITIES:
- Chip integration and netlist generation
- Synthesis
- Netlist quality check
- Formal Verification
- Constraints creation and validation
- Co-work with PR engineers to implement chip partition and floorplan
- Work in conjunction with RR engineers to achieve timing closure for both partition level and full chip level
- Achieve special timing closure, such as io, test, clock etc.
- Function eco creation
- Develop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout)
- Flow automation development
- Methodology in any of above areas.
MINIMUM REQUIREMENTS:
- BSEE, MSEE is preferred
- Project experience in IC design implementation
- Courses taken in circuit design, digital design
- Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (LEC) preferred
- Proficient user of Perl or TCL is preferred
- Excellent English communication skill

Thanks
Sarah

evistera

很好，顶一个

leiya21

很好，投一个，小弟交大微电子硕士。

ljcfcb

很好，本人是西电小硕，投一个试试看