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[讨论] 针对老牛一样慢的仿真,如何把多核的优点发挥出来(讨论)

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发表于 2012-8-30 18:05:33 | 显示全部楼层 |阅读模式

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本帖最后由 小丫 于 2012-8-31 10:39 编辑

如何提高
发表于 2012-8-30 22:16:55 | 显示全部楼层
-mt 8
8核跑起来哦!!
发表于 2015-5-4 09:19:43 | 显示全部楼层
HSPICE Precision Parallel (HPP) technology enables analog and mixed-signal design teams to get the best out of multicore computers for their SPICE simulations by enabling a greater percentage of the simulation to be parallelized. In fact, HPP technology delivers up to 7X simulation speed-up on 8 cores and 10X on 16 cores for analog and mixed-signal designs (see Figure 2). Using HPP technology, design teams can accelerate verification of their analog circuits across process variation corners, meet their project timelines and reduce the risk of silicon respins.

HPP technology is a new multicore transient simulation extension to HSPICE for both pre- and post-layout of complex analog circuits such as PLLs, ADCs, DACs, SerDes, and other full mixed-signal circuits. HPP technology does not compromise HSPICE accuracy. Because HPP technology manages memory efficiently, it has the capacity to simulate post-layout circuits consisting of more than 12 million elements.

Boosting Single-Core Speed
As well as accelerating HSPICE on multicore platforms, HPP technology gives HSPICE simulation a big boost even on single cores.

Today’s analog circuits incorporate components that operate at different time constants. For example, a PLL consists of a voltage-controlled oscillator and divider operating at a high frequency, while other circuit components, such as the phase detector, the filter and the digital control circuitry, operate at much lower speed. The adaptive sub-matrix algorithm in HPP technology manipulates the matrix in such a way that slower parts of the circuit can be solved in fewer iterations than the faster ones, significantly improving the overall simulation speed.

Figure 2 shows the average HSPICE single-core speed improvements over the past five years, alongside other improvements in multicore scalability, capacity, analog analysis features, convergence performance and distributed processing performance. The improvements have resulted in a significant speed-up over the past four years, equivalent to 50X for a 16-core platform.
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