analog power limits paper needed,thanks a lot

shake2004

K. Bult, “Analog design in deep-submicron CMOS,” in Proc. ESSCIRC,
2000, pp. 11–17.
A. J. Annema, “Analog circuit performance and process scaling,” IEEE
Trans. Circuits Syst. II, vol. 46, no. 6, pp. 711–725, 1999.
E. A. Vittoz, “Low-power design:Ways to approach the limits,” in IEEE
Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 1994, pp.
14–18.
“Special issue on scaling limits of gate oxides,” Semicond. Sci. Technol.,
vol. 15, no. 5, 2000.

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shake2004

thanks a lot!