请教多时钟综合的设置

neoitachi · 发表于 2012-8-27 14:18:13

你的这个CLK_2是不是作为port输出了，那样的话咱的现象就一样了，查了一个这个解决方案，但是只讲到mux clock的解决方法，并没有讲到这个的解决方法，你要是有synopsys的账户的话可以进这个网址看看，我没有看不了，希望有人看了能把内容贴出来！https://solvnet.synopsys.com/retrieve/015752.html,大家共同学习一下！

neoitachi · 发表于 2012-8-27 14:21:23

NAME
   PTE-075 (warning) Generated clock '%s' has no path to its master clock.

DESCRIPTION
   The generated clock has no path to the master clock  on  which  it  has
   been  defined. This  may  be  because  there  is no physical path, or
   because the generated clock has been defined as  a  -combinational  and
   the generated clock is not in the direct fanout of the master clock.  A
   propagated source latency of zero will be use from the master clock  to
   the generated clock.

WHAT NEXT
   Please  check  the design and redefine the generated clock to be in the
   fanout of its master clock.

neoitachi · 发表于 2012-8-27 14:22:59

NAME
   UITE-461 (Error) Generated clock '%s' '%s' is not satisfiable%s

DESCRIPTION
   This  is an error  message whenever the clock network traversal can not
   find a path which satisfies the  sense  relationship  defined  by  cre-
   ate_generated_clock command.

WHAT NEXT
   Check  for the generated clock definition to see if the generated clock
   is correctly defined. One example is  that  a  divided_by  2  generated
   clock  is  driven  by  a  inverter  only. In this case, generated clock
   should be redefined with -invert with -divided_by 1. Another  example
   is  a  divided_by  2 generated clock with preinverting. If master clock
   source pin is used as generated clock source pin, PrimeTime will  issue
   the warning message. In this case, generated clock source pin should be
   redefined to clock pin of divider.