使用标准库合成电路时，如果实际电压低于标准电压，怎么办？

loveyahoo

各位前辈：           首先谢谢您的关注。
           小弟是搞模拟电路设计的，最近被老板逼着设计数字电路，使用的标准库是1.8V电压的，
           但是实际电路要在低于1V的电压环境中动作，对于数字合成，我完全是一个新手，试着
           写了Verilog源码，也能合成电路，但合成时所用的延迟参数是基于1.8V的，我不知道合成后
           的电路能否，正常动作？同事说，如果后仿通过的话就没有问题，但我还是不放心，觉得这样做
           太不保险了，不知道各位前辈有什么高见，如果能得到您的指导，小弟将不甚感激！！！

chen.gang.2012

If you have only 1.8v standard cell lib file, it is not guaranteed that the digital part can work under 1v.
You'd better run full transistor simulation for checking its function under 1v.
Anyways, it is impossible to cover all the timing path through simulation. But it is better than doing nothing

loveyahoo

Dear chen.gang.2012：
                               Thanks for your valuable advice. I have no any idea on it , because I am not versed in digital works. So what you have said should be helpful. I will run a full transistor simulation as you suggested. Fortunately, the scale of the circuit is so large. Thanks again, Good luck!

cxl666

transistor simulation时间太久，而且未必能够仿真的（看testbench好写不了），可以用foundry提供的1V电源的时序库，如果没有的话可以自己做一个的，这样保证signoff，后仿通过就可以了。

loveyahoo

谢谢4楼cxl666的高见， 的确晶体管曾的仿真很慢。 很遗憾的是我的foundry没有提供1V的电源时序， 我也没有写时序库的经验。 不知道有没有这方面的资料或者是网站之类的也可以啊，恳请赐教！

chen.gang.2012

How is it going?
Which tool are you using for the simulation?
Keep in mind that any dynamic simulation cannot cover all timing path.
You may need plan the stimulus well.

Another way is
Compare the timing between 1.8v and 1v through the transistor simulation in high accurate mode.
Then you will get idea how much worse the timing of each cell becomes.
Then you can use 1.8 lib to do the STA, but with more clock skew to compansate the worse timing.