COMPLETE DIGITAL DESIGN

fancy77

LBSALE[20]LBSALECOMPLETE DIGITAL DESIGN
A Comprehensive Guide to Digital Electronics and Computer System Architecture
Mark Balch
CONTENTS
PART 1 Digital Fundamentals
Chapter 1 Digital Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Boolean Logic /
1.2 Boolean Manipulation /
1.3 The Karnaugh map /
1.4 Binary and Hexadecimal Numbering /
1.5 Binary Addition /
1.6 Subtraction and Negative Numbers /
1.7 Multiplication and Division /
1.8 Flip-Flops and Latches /
1.9 Synchronous Logic /
1.10 Synchronous Timing Analysis /
1.11 Clock Skew /
1.12 Clock Jitter /
1.13 Derived Logical Building Blocks /
Chapter 2 Integrated Circuits and the 7400 Logic Families. . . . . . . . . . . . . . . . . . . . .33
2.1 The Integrated Circuit /
2.2 IC Packaging /
2.3 The 7400-Series Discrete Logic Family /
2.4 Applying the 7400 Family to Logic Design /
2.5 Synchronous Logic Design with the 7400 Family /
2.6 Common Variants of the 7400 Family /
2.7 Interpreting a Digital IC Data Sheet /
Chapter 3 Basic Computer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
3.1 The Digital Computer /
3.2 Microprocessor Internals /
3.3 Subroutines and the Stack /
3.4 Reset and Interrupts /
3.5 Implementation of an Eight-Bit Computer /
3.6 Address Banking /
3.7 Direct Memory Access /
3.8 Extending the Microprocessor Bus /
3.9 Assembly Language and Addressing Modes /
Chapter 4 Memory
4.1 Memory Classifications /
4.2 EPROM /
4.3 Flash Memory /
4.4 EEPROM /
4.5 Asynchronous SRAM /
4.6 Asynchronous DRAM /
4.7 Multiport Memory /
4.8 The FIFO /
Chapter 5 Serial Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
5.1 Serial vs. Parallel Communication /
5.2 The UART /
5.3 ASCII Data Representation /
5.4 RS-232 /
5.5 RS-422 /
5.6 Modems and Baud Rate /
5.7 Network Topologies /
5.8 Network Data Formats /
5.9 RS-485 /
5.10 A Simple RS-485 Network /
5.11 Interchip Serial Communications /
Chapter 6 Instructive Microprocessors and Microcomputer Elements . . . . . . . . . .121
6.1 Evolution /
6.2 Motorola 6800 Eight-bit Microprocessor Family /
6.3 Intel 8051 Microcontroller Family /
6.4 Microchip PIC  Microcontroller Family /
6.5 Intel 8086 16-Bit Microprocessor Family /
6.6 Motorola 68000 16/32-Bit Microprocessor Family /
PART 2 Advanced Digital Systems
Chapter 7 Advanced Microprocessor Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
7.1 RISC and CISC /
7.2 Cache Structures /
7.3 Caches in Practice /
7.4 Virtual Memory and the MMU /
7.5 Superpipelined and Superscalar Architectures /
7.6 Floating-Point Arithmetic /
7.7 Digital Signal Processors /
7.8 Performance Metrics /
Chapter 8 High-Performance Memory Technologies. . . . . . . . . . . . . . . . . . . . . . . . .173
8.1 Synchronous DRAM /
8.2 Double Data Rate SDRAM /
8.3 Synchronous SRAM /
8.4 DDR and QDR SRAM /
8.5 Content Addressable Memory /
Chapter 9 Networking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
9.1 Protocol Layers One and Two /
9.2 Protocol Layers Three and Four /
9.3 Physical Media /
9.4 Channel Coding /
9.5 8B10B Coding /
9.6 Error Detection /
9.7 Checksum /
9.8 Cyclic Redundancy Check /
9.9 Ethernet /
Chapter 10 Logic Design and Finite State Machines . . . . . . . . . . . . . . . . . . . . . . . . .221
10.1 Hardware Description Languages /
10.2 CPU Support Logic /
10.3 Clock Domain Crossing /
10.4 Finite State Machines /
10.5 FSM Bus Control /
10.6 FSM Optimization /
10.7 Pipelining /
Chapter 11 Programmable Logic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
11.1 Custom and Programmable Logic /
11.2 GALs and PALs /
11.3 CPLDs /
11.4 FPGAs /
PART 3 Analog Basics for Digital Systems
Chapter 12 Electrical Fundamentals  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
12.1 Basic Circuits /
12.2 Loop and Node Analysis /
12.3 Resistance Combination /
12.4 Capacitors /
12.5 Capacitors as AC Elements /
12.6 Inductors /
12.7 Nonideal RLC Models /
12.8 Frequency Domain Analysis /
12.9 Lowpass and Highpass Filters /
12.10 Transformers /
Chapter 13 Diodes and Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
13.1 Diodes /
13.2 Power Circuits with Diodes /
13.3 Diodes in Digital Applications /
13.4 Bipolar Junction Transistors /
13.5 Digital Amplification with the BJT /
13.6 Logic Functions with the BJT /
13.7 Field-Effect Transistors /
13.8 Power FETs and JFETs /
Chapter 14 Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
14.1 The Ideal Op-amp /
14.2 Characteristics of Real Op-amps /
14.3 Bandwidth Limitations /
14.4 Input Resistance / 325
14.5 Summation Amplifier Circuits / 328
14.6 Active Filters / 331
14.7 Comparators and Hysteresis / 333
Chapter 15 Analog Interfaces for Digital Systems. . . . . . . . . . . . . . . . . . . . . . . . . . .339
15.1 Conversion between Analog and Digital Domains / 339
15.2 Sampling Rate and Aliasing / 341
15.3 ADC Circuits / 345
15.4 DAC Circuits / 348
15.5 Filters in Data Conversion Systems / 350
PART 4 Digital System Design in Practice
Chapter 16 Clock Distribution  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
16.1 Crystal Oscillators and Ceramic Resonators / 355
16.2 Low-Skew Clock Buffers / 357
16.3 Zero-Delay Buffers: The PLL / 360
16.4 Frequency Synthesis / 364
16.5 Delay-Locked Loops / 366
16.6 Source-Synchronous Clocking / 367
Chapter 17 Voltage Regulation and Power Distribution . . . . . . . . . . . . . . . . . . . . . .371
17.1 Voltage Regulation Basics / 372
17.2 Thermal Analysis / 374
17.3 Zener Diodes and Shunt Regulators / 376
17.4 Transistors and Discrete Series Regulators / 379
17.5 Linear Regulators / 382
17.6 Switching Regulators / 386
17.7 Power Distribution / 389
17.8 Electrical Integrity / 392
Chapter 18 Signal Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
18.1 Transmission Lines / 398
18.2 Termination / 403
18.3 Crosstalk / 408
18.4 Electromagnetic Interference / 410
18.5 Grounding and Electromagnetic Compatibility / 413
18.6 Electrostatic Discharge / 415
Chapter 19 Designing for Success . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419
19.1 Practical Technologies / 420
19.2 Printed Circuit Boards / 422
19.3 Manually Wired Circuits / 425
19.4 Microprocessor Reset / 428
19.5 Design for Debug / 429
19.6 Boundary Scan / 431
19.7 Diagnostic Software / 433
19.8 Schematic Capture and Spice / 436
19.9 Test Equipment / 440
Appendix A Further  . . . . . . . . . . . . . . . . .443

shadow

不错不错，搞下来看看

shadow

为什么下不下来

tghtgl

kan  buliao a

pedro789

good ebook///

escortid

thank you so much

escortid

2003年版，正是我想要的，再谢。

MooM

好像不错，不过有没有68000 family assembly language 这个资料啊？

henry1981525

IC设计经典之作：digital system clocking