关于ram 的testbench 编写

zhaow0422

各位好 我现在设计了一个ram, 读数据的时候，地址是另外单独控制的， 这个我不清楚testbench 怎么写，谁能帮助一下
以下是ram 的verilog code

module memory_256(addr, data_in, data_out, write, read, clk_sys, rst
    );
input [7:0]
addr;
//256 address
input [7:0]
data_in;
// 8 bit
input write, read, clk_sys, rst;
output [7:0]
data_out;

reg [7:0]
data_out;
reg [7:0]
memory [255:0];
wire [7:0]
addr;

integer i;
// asynchronous reset
always @(posedge clk_sys or posedge rst)
begin

if(rst)

begin

data_out <= 0;

for (i=0;i<255;i=i+1)

memory <= 0;

end

else

begin

if(read)

data_out <= memory [addr];

else if (write)

begin

data_out <= 0;

memory [addr] <= data_in;

end

end
end

//===============================How many column in one MB============================

reg         [3:0]
r_col_address;

reg
[1:0]
r_blk_col_cnt;


wire
[1:0]
s_blk_col_cnt;

  

always @(posedge clk_sys or posedge rst)

if(rst == 1'b1)

r_blk_col_cnt <= 0;

else if(r_blk_col_cnt == 3)

r_blk_col_cnt <= 0;

else if(r_blk_col_cnt < 3)

r_blk_col_cnt <= r_blk_col_cnt + 1;



assign
s_blk_col_cnt = r_blk_col_cnt;



//==============================How many macroblock in Horizontal============================

reg
[1:0]
r_blk_num_h;

wire
[1:0]
s_blk_num_h;





always @(posedge clk_sys or posedge rst)

if(rst == 1'b1)

r_blk_num_h <= 0;


else

  begin

if(r_blk_num_h == 3)


r_blk_num_h <= 0;

else if(s_one_block_finish == 1'b1)

begin

if(r_blk_num_h < 3)

r_blk_num_h <= r_blk_num_h + 1;

else

r_blk_num_h <= 0;

end


  end





assign s_blk_num_h = r_blk_num_h;



//================================address in horizontal direction=======================================

wire
[3:0]
s_address_h;

assign
s_address_h = {s_blk_num_h,s_blk_col_cnt};



//==============================how many row in one MB==========================================

reg
[1:0]
r_blk_row_cnt;

wire
[1:0]
s_blk_row_cnt;



always @(posedge clk_sys or posedge rst)

if(rst == 1'b1)

r_blk_row_cnt <= 0;

else if(r_blk_row_cnt == 3)

r_blk_row_cnt <= 0;

else

r_blk_row_cnt <= r_blk_row_cnt + 1;





assign
s_blk_row_cnt = r_blk_row_cnt;



//=============================how many macroblock in one vertical=================================

reg
[1:0]
r_blk_num_v;

wire
[1:0]
s_blk_num_v;



always @(posedge clk_sys or posedge rst)

if(rst == 1'b1)

r_blk_num_v <= 0;

else if(r_blk_num_h == 3)

begin


if(r_blk_num_v < 3)

r_blk_num_v <= r_blk_num_v + 1;

else

r_blk_num_v <= 0;

end

else r_blk_num_v <= 0;



assign
s_blk_num_v = r_blk_num_v;



//=============== ============address in vertical direction==================================================



wire
[3:0]
s_address_v;

assign
s_address_v = {r_blk_num_v, r_blk_row_cnt};



//===========================address of pixel in the frame===========================================

//wire
[7:0]
addr;
   assign
addr = {s_address_v,s_address_h};


endmodule


一下是普通ram读写的testbench
module memory_256_tb(
    );
wire [7:0]
address, addr;
reg [7:0]
data, data_in;
reg
write, read, clk_sys, rst;
wire s_one_block_finish;

wire [7:0]
data_out;

parameter cycle = 20;

integer i;
initial
begin

addr = 0;

rst = 0;

read = 0;

write = 0;

data_in = 0;

clk_sys = 0;

forever #20 clk_sys = ~clk_sys;
end

initial
begin

//for reset

rst = 0;

#cycle;

rst = 1;

#cycle;

rst = 50;

#cycle;



for (i=0;i<255;i=i+1)

begin

address = i;

data = i;

memory_write(address, data);

#cycle;

end

for(i=255;i>0;i=i-1)

begin

address = i;

memory_read(address);

#cycle;

end

$stop;
end

task memory_write;
input [7:0] data;
input [7:0]
address;
begin

addr = address;

data_in = data;

write = 0;

#cycle;

write = 1;

read = 0;

repeat (2) #cycle;

write = 0;

#cycle;

$display ("Completed writing data %h at address %h", data_in, addr);
end
endtask

task memory_read;
input [7:0] address;
begin

read = 0;

addr = address;

data_in = 0;

#cycle;

read = 1;

repeat (2) #cycle;

read = 0;

#cycle;

$display ("Completed reading memory at address %h. Data is %h", addr, data_out);
end
endtask

endmodule

duan_dzj

没看懂，等高手解释！

SKILLER

地址是另外单独控制的
那应该就根据你验证需要来编写它的地址输入啊
代码太长，没看

zhaow0422

回复 3# SKILLER
感谢你的回答
你的意思 就是专门编写testbench 去验证地址了？

SKILLER

回复 4# zhaow0422


    对啊，你的设计要证明是正确的，你就应该给它一定激励信号，验证输出是否与期望值相同

zhaow0422

回复 5# SKILLER


  明白了，谢谢了，我起初打算把memory 跟地址一起验证 ，把memory 作为源，去读数据，现在明白了 分开来 保证memory 读写正确 地址控制正确 谢谢