计数计数模块设计遇到的问题

woshaogang123

回复 9# chenfengrugao


    我在Quartus II 里面建波形文件怎么仿真不出来呢?

chenfengrugao

回复 10# woshaogang123

那你需要先取start和stop的上升沿。
因为逻辑简单，就根据start和stop的上升沿产生计数的状态（cnt_status）。复杂时用状态机。
QuartusII不能仿真的原因不是很清楚，应该是软件没设置好，建议再看看帮助文档。我这里没有QuartusII所以没法给你截图。

下面是参考代码。
   

1. library ieee;
   
2. use ieee.std_logic_1164.all;
   
3. use ieee.std_logic_unsigned.all;
   
4. 
   
5. entity count is
   
6. port(
   
7. clk:in std_logic;
   
8. reset : in std_logic;
   
9. start: in std_logic;
   
10. stop: in std_logic;
    
11. cout : out std_logic_vector(7 downto 0)
    
12. );
    
13. end count;
    
14. 
    
15. architecture behav of count is
    
16. signal start_dly1 : std_logic;
    
17. signal start_dly2 : std_logic;
    
18. signal start_rising_edge : std_logic;
    
19. signal stop_dly1 : std_logic;
    
20. signal stop_dly2 : std_logic;
    
21. signal stop_rising_edge : std_logic;
    
22. signal cnt_status : std_logic;
    
23. begin
    
24. 
    
25. process(clk,reset)
    
26. begin
    
27. if reset='1' then
    
28. start_dly1 <= '0';
    
29. start_dly2 <= '0';
    
30. elsif clk'event and clk='1' then
    
31. start_dly1 <= start;
    
32. start_dly2 <= start_dly1;
    
33. end if;
    
34. end process;
    
35. 
    
36. start_rising_edge <= not(start_dly2) and start_dly1;
    
37. 
    
38. process(clk,reset)
    
39. begin
    
40. if reset='1' then
    
41. stop_dly1 <= '0';
    
42. stop_dly2 <= '0';
    
43. elsif clk'event and clk='1' then
    
44. stop_dly1 <= stop;
    
45. stop_dly2 <= stop_dly1;
    
46. end if;
    
47. end process;
    
48. 
    
49. stop_rising_edge <= not(stop_dly2) and stop_dly1;
    
50. 
    
51. -- status
    
52. process(clk,reset)
    
53. begin
    
54. if reset='1' then
    
55. cnt_status <= '0';
    
56. elsif clk'event and clk='1' then
    
57. if start_rising_edge = '1' then
    
58. cnt_status <= '1';
    
59. elsif stop_rising_edge = '1' then
    
60. cnt_status <= '0';
    
61. end if;
    
62. end if;
    
63. end process;
    
64. 
    
65. process(clk,reset)
    
66. variable c : std_logic_vector(7 downto 0);
    
67. begin
    
68. if reset='1' then
    
69. c:="00000000";
    
70. cout<="00000000";
    
71. elsif clk'event and clk='1' then
    
72. if cnt_status = '1' then
    
73. c:=c+1;
    
74. else
    
75. cout<=c;
    
76. end if;
    
77. end if;
    
78. end process;
    
79. 
    
80. end behav;
    
81. 
    
82. 
    

复制代码