求 DesignWare DDR2/3-Lite Memory Controller IP

sigurd · 发表于 2012-6-7 14:40:26

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Does anyone provide DesignWare DDR2/3-Lite Memory Controller IP?
The Synopsys DesignWare® DDR2/3-Lite SDRAM Memory Controller IP (MCTL) offers an efficient digital interface between up to 32 on-chip application buses and a DDR2/3-Lite physical layer (PHY) in a DDR3 or DDR2 memory subsystem. The MCTL is a full-featured memory controller that provides efficient DDR control and protocol translation, support for multiple application ports, quality of service (QoS) control and optimized memory transaction scheduling. The MCTL also handles all initialization tasks for the memory subsystem including DRAM initialization and PHY data training.

http://www.synopsys.com/dw/ipdir.php?ds=dwc_ddr2-lite_mem

xwave · 发表于 2012-7-16 21:41:05

这是讲工艺么？

sigurd · 发表于 2012-7-17 08:57:25

No, it's DRAM controller.

netking · 发表于 2013-1-12 15:16:42

本帖最后由 netking 于 2013-1-16 11:38 编辑

Thanks..for the Info.

Thanks..

netking · 发表于 2013-1-16 11:27:53

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ddale · 发表于 2013-2-14 16:29:38

这个是要花很多咪咪的。。。
过年来赚钱！！！

bananawolf · 发表于 2013-2-15 00:29:20

eetop good

yameide18 · 发表于 2013-3-6 10:14:52

回复 1# sigurd

能发我一份么。

asp200 · 发表于 2013-3-15 13:35:20

有IP Library可分享嗎?

hbyu · 发表于 2013-4-25 23:06:08

这个能找到吗？

求 DesignWare DDR2/3-Lite Memory Controller IP

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