用verilog实现RS(204,188)译码器 没有输出，请教高手

wqm0716

module SCalculate(clk, init, sc_done, r, s_out);

parameter
t = 8,
// t--The total number of errors that can be corrected

N = 204,
// N--Codeword length

m = 8;
// m--Extension of GF(2)



input
clk, init;

input [m-1:0]
r;

output[m-1:0]
s_out;

output
sc_done;



reg  [m-1:0] s[t*2:1], s_latched[t*2:1];

wire [m-1:0] r_a[t*2:1];

integer
counter;

always @(posedge clk)

begin

integer j;j=0;

if((init) || (counter==N))begin

for(j=1; j<=t*2; j=j+1)
// Latch the last syndrome sequences

s_latched[j] <= s[j];
     for(j=1; j<=t*2; j=j+1)           

              s[j] <= r;

counter<=1;



end

else if(counter<N)begin

for(j=1; j<=t*2; j=j+1)

s[j] <= r ^ r_a[j];

counter <= counter + 1;

end

end



ff_const_mul r_x_a1(.din(s[1]), .dout(r_a[1]));
// a^1

ff_const_mul r_x_a2(.din(s[2]), .dout(r_a[2]));
// a^2

ff_const_mul r_x_a3(.din(s[3]), .dout(r_a[3]));
// a^3

ff_const_mul r_x_a4(.din(s[4]), .dout(r_a[4]));
// a^4

ff_const_mul r_x_a5(.din(s[5]), .dout(r_a[5]));
// a^5

ff_const_mul r_x_a6(.din(s[6]), .dout(r_a[6]));
// a^6

ff_const_mul r_x_a7(.din(s[7]), .dout(r_a[7]));
// a^7

ff_const_mul r_x_a8(.din(s[8]), .dout(r_a[8]));
// a^8

ff_const_mul r_x_a9(.din(s[9]), .dout(r_a[9]));
// a^9

ff_const_mul r_x_a10(.din(s[10]), .dout(r_a[10]));
// a^10

ff_const_mul r_x_a11(.din(s[11]), .dout(r_a[11]));
// a^11

ff_const_mul r_x_a12(.din(s[12]), .dout(r_a[12]));
// a^12

ff_const_mul r_x_a13(.din(s[13]), .dout(r_a[13]));
// a^13

ff_const_mul r_x_a14(.din(s[14]), .dout(r_a[14]));
// a^14

ff_const_mul r_x_a15(.din(s[15]), .dout(r_a[15]));
// a^15

ff_const_mul r_x_a16(.din(s[16]), .dout(r_a[16]));
// a^16

defparam r_x_a1.CONST  = 16'h4405;

defparam r_x_a2.CONST  = 16'h6202,
r_x_a3.CONST  = 16'h7101,

r_x_a4.CONST  = 16'h3880,
r_x_a5.CONST  = 16'h1C40,

r_x_a6.CONST  = 16'h0E20,
r_x_a7.CONST  = 16'h4710,

r_x_a8.CONST  = 16'h2388,
r_x_a9.CONST  = 16'h11C4,

r_x_a10.CONST  = 16'h48E2,
r_x_a11.CONST = 16'h2471,

r_x_a12.CONST = 16'h5238,
r_x_a13.CONST = 16'h691C,

r_x_a14.CONST = 16'h748E,
r_x_a15.CONST = 16'h3A47,

r_x_a16.CONST = 16'h1D23;


reg

sc_done;

integer
shift_count;


always @(posedge clk)begin

if(counter == N)begin

sc_done <= 1;

shift_count <= 1;

end

else begin

sc_done <= 0;

if((0<shift_count) && (shift_count <= t*2))

begin

shift_count <= shift_count + 1;

end

else

shift_count <= 0;

end

end


reg [m-1:0] s_out;

always @(shift_count)begin

if((0<shift_count) &&(shift_count <= t*2))

s_out = s_latched[shift_count];

else

s_out = 0;

end


endmodule
这个设置了时钟信号和输入，但是没有输出。请高手看看是哪里的问题

wqm0716

自己顶，求高手啊，高手在哪里。