AMD招聘集成电路设计及验证工程师

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AMD招聘集成电路设计及验证工程师，

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Maggie1.Zhang@amd.com
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1.Senior/ Staff engineer for IC verification

Requirements:

The candidate is preferred to be MSEE with minimum of 3 years, or BSEE with minimum of 5 years experience in digital asic/SOC design verification.
The candidate should have good understanding on ASIC/SOC design flow and should have:

1.       Good knowledge of design verification methodology, such as VMM or OVM.

2.       Many experiences with simulation model creation and the testbench build

3.       Strong RTL coding with verilog and familiar with front-end design flow

4.       Strong C/C++ software development experiences

5.       Be familiar with scripting language, such as Perl, C shell, Makefile.

It is a plus if the candidate has one or more of the following experience/knowledge, such as X86/arm/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.

Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.

The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability
to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.

Responsibility:

The successful candidate will apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC design.
He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.

2.Senior/MTS engineer for IC design

Senior engineer for IC design engineering (Sr. DE)

Requirements:

The candidate is preferred to be MSEE with minimum of 3 years, or BSEE with minimum of 5 years experience in digital ASIC/SOC design engineering.
The candidate should have good understanding on ASIC/SOC design flow and must be proficient in two or more of the following skill sets:

1.       RTL(verilog) coding and style checking

2.       scripts based on makefile, perl, TCL or csh/tcsh

3.       clock-domain-cross checking

4.       dynamic logic simulation or post-layout simulation

5.       logic synthesis or physical Synthesis

6.       static timing analysis

7.       logic equivalency checking

8.       ECO(engineering change order)

9.       top level integration, floor planning, pad-ring design

10.   clock distribution

11.   design for test, design for debug or design for power

It is a plus if the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.

Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.

The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability
to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.

Responsibility:

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: specification, top level SOC design tasks, hdl coding, synthesis, timing closure, etc. The job may require some lab bring up and debugging of the reference board system after the tape-out chip comes back.

3.Systems Engineering Manager

As a manager of the SRDC Systems Engineering team, you will be responsible for leading an engineering team through the development cycles of the latest SOC’s and IP’s for AMD’s Fusion APU’s and DGPU’s. The successful candidate will be managing a hardware engineering team consisting of Silicon Bring-up Leads and IP Systems Engineers during pre-silicon planning, post-silicon bring-up, validation and production ramp.

Your team will be involved in the pre-silicon and post-silicon phases of the design. In the pre-silicon phase, you will manage the team as they plan and develop creative solutions to meet aggressive post-silicon schedules while working intimately with silicon design engineering and platform design teams. In the post-silicon phase, you will lead the systems engineering team through the various phases of bring-up, validation and production ramp. Your team will also occasionally assist in customer design issues. In essence, your team will be the link between design and physical silicon.

This is a global team. The successful candidate will work globally with management in North America and other geographies to align team priorities, resources and skill sets.

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Experience:

A B. Sc. in Electrical/Computer Engineering and minimum 5 years of work experience is required.

This position requires a candidate with a strong technical background in PC systems and graphics. Strong leadership, management, critical thinking, analytical and organizational skills are a must.

Excellent communication skills (both verbal and written) are required for writing reports and e-mails and conducting meetings.

4.Design Verification Manager for Graphics Hardware

Position Summary

In this key role, the candidate will be managing a design verification team in the development of infrastructure for validation of architectures and verification of hardware.

Essential Functions:

• Development of infrastructure for verification of hardware in GFX IP.
• Low power design and verification for specific hardware functionality in Front-end.
• Bring-up support and post-silicon power validation.
• Develop verification environments for feature verification, and use the automated regression infrastructure setup for IP level and IP on SoC level functional verification.

Requirements/Qualifications:

• BS, MS or PhD in Computer Science or Electrical Engineering.
• 8+ years of ASIC verification or low power design experience
• Should have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release.
• Advanced programming knowledge on Verilog/SystemVerilog, C/C++
• Requires demonstrated technical expertise in the areas of Design Verification and low power design/verification methodology.
• Knowledge on Perforce, OVL, SVA, SV, UVM, script programming etc.
• Should have excellent communication skills (both written and oral) and should be able to participate cross functional engineering teams geographically.
• Demonstrates leadership ability preferred.

Skills/Competencies:

·         Good design verification experience

·         Good communication

·         Strong problem solving skills

·         Low power design verification or computer graphics knowledge are plus

Desired:

·         Team Lead experience

·         Design Verification experience