在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 2389|回复: 2

[求助] dc 综合时min_capacitance violation

[复制链接]
发表于 2012-4-10 09:37:32 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
Hi, all,

I learned from the DC User Guide that the min_capacitance is a constraint set on an input or bidirectional port, however, the tool issued a min_capacitance violation when I try to constraint an output port with the following constraint:
set_load -max 10.0 [get_ports OUT_PORT1]
set_load -min 0.01 [get_ports OUT_PORT1]
and with no set_min_capacitance on any ports.

I checked the library and found that the library did have both the max & min capacitance constraint for the output pin of that cell:
max_capacitance: 145
min_capacitance: 10

and this indeed explain why DC issues an -9.99(0.01 - 10) min_capacitance negative slack, however, I couldn't figure out why the library have an min_capacitance constraint on an output pins of a certain cell, and how should I fix this violation. In my opinion, it's invalid to simply use set_load -min 10(or a higher value) [get_ports OUT_PORT1], how should I constraint the load on this output port OUT_PORT1

sincerely 3ks in advance.

BR,
henry
 楼主| 发表于 2012-4-10 20:23:53 | 显示全部楼层
回复 2# zhq415758192


好的,多谢哈.
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /2 下一条


小黑屋| 手机版| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-11-26 06:21 , Processed in 0.017999 second(s), 8 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表