【Marvell招聘】 COMMON LAB 部门招聘

tiaxiadiyihei

【Marvell招聘】 COMMON LAB 部门招聘

If you have any interest in the position, please send your bilingual resume as attachments to
marvell.recruit@gmail.com Subject of your email should be “Your Name_University_Applied Position Title”

1、Job Title : (Senior) Circuit Design Engineer

Department :COT Common Lab

Location
: Shanghai

Job Description

Design, evaluate, and improve standard cell library architectures for tradeoffs in size, speed, density and yield for targeted applications. Investigate advanced technology layout dependent effects and their impact on performance for high speed library design.

The candidate will help bring up local transistor level layout team that will concentrate on realizing circuit design and technology trade-offs for library performance improvement.
They will have close interaction and supervision of the layout designers to meet desired design parameters.

Qualifications

-BSEE with more than 5 years of experience or MSEE with 3 or more years of experience, in standard cell circuit design or relevant industrial experience.

-The candidate should be well versed in Hspice or equivalent circuit simulation as well as full custom design layout software.

-Experience in cutting edge technology nodes 32nm and below a plus.

-Excellent Perl and Unix shell scripting skills for design automation and analysis are required.

-Looking for a disciplined and methodical worker with a creative and inquiring mindset.

-The applicant should have clear English written and verbal communication skills.

-Management lead experience a plus.

2、Job Title:
(Senior) Layout Design Engineer

Department: COT Common Lab

Location:
Shanghai

Job Description:

Improve standard cell library layout architectures for tradeoffs in size, speed, density and yield for targeted applications.
The designer will be working on cutting edge process nodes, helping review locally generated layouts for efficient implementation before release to central team.
The designer should have a clear understanding of standard cell layout constraints and be able to drive trade-offs and new rule creation.

The candidate will be working closely with circuit design to help optimize standard cells, and complete libraries, to take advantage of cutting edge layout dependent effects to improve the overall library performance.

Qualifications:

-BSEE with more than 5 years of experience or MSEE with 3 or more years of experience

-Standard cell layout expertise with 3 or more years of relevant industrial experience.

-Cutting edge, 32nm and below technology node experience a plus.

-The candidate should be proficient with transistor level layout and related tools such as Cadence virtuoso or Springsoft Laker, as well as Calibre DRC/LVS or equivalent tool set.

-They should have experience running the complete layout design flow including schematic to layout generation, DRC, LVS, ERC and DFM verification and validation.

-Experience in parasitic extraction a plus.

-Looking for a disciplined and methodical worker with a creative and inquiring mindset.

-The applicant should have clear English written and verbal communication skills.

-Lead experience a plus.