LegUp high-level synthesis tool 2.0

jintan12 · 发表于 2012-4-1 18:54:29

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本帖最后由 jintan12 于 2012-4-1 18:55 编辑

LegUp is a high-level synthesis tool for C to Verilog synthesis.

LegUp accepts a ANSI C file as input, no pragmas or special keywords are required, and produces a Verilog hardware description file as output that can be synthesized onto an Altera FPGA.

Any C printf statements are converted to Verilog $display statements that are printed during a modelsim simulation, making it possible to compile the same C file with gcc and check its output against the simulation.

LegUp has two different synthesis flows:

Pure hardware: Synthesizes the whole C file into hardware with no soft processor
Hybrid: Execute a portion of the C file on the TigerMIPS soft processor and synthesize the rest into hardware

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