FPGA对DDRSDRAM的管脚分配问题

mingtian2010

如下使用的是Cyclone III：EP3C16F484C6
分配给DDRSDRAM的管脚安排对应如最右一列所示，
在Quartus II 9.0上建立工程生产一个DDRSDRAM的IP核，
直接用此核上带的例程：ddr_example_top，按照下面的来分配管脚
分析综合能过，但是Fitter（Place & Route）时有如下错误：
请问是什么原因？是我管脚分配错误吗？那要怎样分配啊！
万分感谢！！！

Error: Can't place pin mem_clk[0] to location AA3
Error: Can't place VREF pin Y4 (VREFGROUP_B3_N1) for pin mem_clk[0] of type bi-directional with SSTL-2 Class I I/O standard at location AA3
  Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 3 when the VREF pin Y4 (VREFGROUP_B3_N1) is used on device EP3C16F484C6 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
   Info: Location R9 (pad PAD_88): Pin mem_addr[0] of type output uses SSTL-2 Class I I/O standard
   Info: Location T8 (pad PAD_89): Pin mem_addr[1] of type output uses SSTL-2 Class I I/O standard
   Info: Location R10 (pad PAD_90): Pin mem_addr[2] of type output uses SSTL-2 Class I I/O standard
   Info: Location T9 (pad PAD_91): Pin mem_addr[3] of type output uses SSTL-2 Class I I/O standard
   Info: Location V6 (pad PAD_92): Pin mem_addr[4] of type output uses SSTL-2 Class I I/O standard
   Info: Location V5 (pad PAD_93): Pin mem_dm[0] of type output uses SSTL-2 Class I I/O standard
   Info: Location U7 (pad PAD_94): Pin mem_addr[5] of type output uses SSTL-2 Class I I/O standard
   Info: Location U8 (pad PAD_95): Pin mem_addr[6] of type output uses SSTL-2 Class I I/O standard
   Info: Location R11 (pad PAD_97): Pin mem_addr[7] of type output uses SSTL-2 Class I I/O standard
   Info: Location R12 (pad PAD_98): Pin mem_addr[8] of type output uses SSTL-2 Class I I/O standard
   Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
    Info: Location R9 (pad PAD_88): Pin mem_addr[0] of type output uses SSTL-2 Class I I/O standard
    Info: Location T8 (pad PAD_89): Pin mem_addr[1] of type output uses SSTL-2 Class I I/O standard
    Info: Location R10 (pad PAD_90): Pin mem_addr[2] of type output uses SSTL-2 Class I I/O standard
    Info: Location T9 (pad PAD_91): Pin mem_addr[3] of type output uses SSTL-2 Class I I/O standard
    Info: Location V6 (pad PAD_92): Pin mem_addr[4] of type output uses SSTL-2 Class I I/O standard
    Info: Location V5 (pad PAD_93): Pin mem_dm[0] of type output uses SSTL-2 Class I I/O standard
    Info: Location U7 (pad PAD_94): Pin mem_addr[5] of type output uses SSTL-2 Class I I/O standard
    Info: Location U8 (pad PAD_95): Pin mem_addr[6] of type output uses SSTL-2 Class I I/O standard
    Info: Location Y4 (pad PAD_96): unused
    Info: Location R11 (pad PAD_97): Pin mem_addr[7] of type output uses SSTL-2 Class I I/O standard
    Info: Location R12 (pad PAD_98): Pin mem_addr[8] of type output uses SSTL-2 Class I I/O standard
    Info: Location Y3 (pad PAD_99): unused
Error: Can't place pin mem_clk_n[0] to location AB3
Error: Can't place VREF pin Y4 (VREFGROUP_B3_N1) for pin mem_clk_n[0] of type bi-directional with SSTL-2 Class I I/O standard at location AB3
  Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 3 when the VREF pin Y4 (VREFGROUP_B3_N1) is used on device EP3C16F484C6 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
   Info: Location R9 (pad PAD_88): Pin mem_addr[0] of type output uses SSTL-2 Class I I/O standard
   Info: Location T8 (pad PAD_89): Pin mem_addr[1] of type output uses SSTL-2 Class I I/O standard
   Info: Location R10 (pad PAD_90): Pin mem_addr[2] of type output uses SSTL-2 Class I I/O standard
   Info: Location T9 (pad PAD_91): Pin mem_addr[3] of type output uses SSTL-2 Class I I/O standard
   Info: Location V6 (pad PAD_92): Pin mem_addr[4] of type output uses SSTL-2 Class I I/O standard
   Info: Location V5 (pad PAD_93): Pin mem_dm[0] of type output uses SSTL-2 Class I I/O standard
   Info: Location U7 (pad PAD_94): Pin mem_addr[5] of type output uses SSTL-2 Class I I/O standard
   Info: Location U8 (pad PAD_95): Pin mem_addr[6] of type output uses SSTL-2 Class I I/O standard
   Info: Location R11 (pad PAD_97): Pin mem_addr[7] of type output uses SSTL-2 Class I I/O standard
   Info: Location R12 (pad PAD_98): Pin mem_addr[8] of type output uses SSTL-2 Class I I/O standard
   Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
    Info: Location R9 (pad PAD_88): Pin mem_addr[0] of type output uses SSTL-2 Class I I/O standard
    Info: Location T8 (pad PAD_89): Pin mem_addr[1] of type output uses SSTL-2 Class I I/O standard
    Info: Location R10 (pad PAD_90): Pin mem_addr[2] of type output uses SSTL-2 Class I I/O standard
    Info: Location T9 (pad PAD_91): Pin mem_addr[3] of type output uses SSTL-2 Class I I/O standard
    Info: Location V6 (pad PAD_92): Pin mem_addr[4] of type output uses SSTL-2 Class I I/O standard
    Info: Location V5 (pad PAD_93): Pin mem_dm[0] of type output uses SSTL-2 Class I I/O standard
    Info: Location U7 (pad PAD_94): Pin mem_addr[5] of type output uses SSTL-2 Class I I/O standard
    Info: Location U8 (pad PAD_95): Pin mem_addr[6] of type output uses SSTL-2 Class I I/O standard
    Info: Location Y4 (pad PAD_96): unused
    Info: Location R11 (pad PAD_97): Pin mem_addr[7] of type output uses SSTL-2 Class I I/O standard
    Info: Location R12 (pad PAD_98): Pin mem_addr[8] of type output uses SSTL-2 Class I I/O standard
    Info: Location Y3 (pad PAD_99): unused
Error: Can't place pin mem_dq[0] to location Y3
Error: Can't place VREF pin Y4 (VREFGROUP_B3_N1) for pin mem_dq[0] of type bi-directional with SSTL-2 Class I I/O standard at location Y3
  Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 3 when the VREF pin Y4 (VREFGROUP_B3_N1) is used on device EP3C16F484C6 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
   Info: Location R9 (pad PAD_88): Pin mem_addr[0] of type output uses SSTL-2 Class I I/O standard
   Info: Location T8 (pad PAD_89): Pin mem_addr[1] of type output uses SSTL-2 Class I I/O standard
   Info: Location R10 (pad PAD_90): Pin mem_addr[2] of type output uses SSTL-2 Class I I/O standard
   Info: Location T9 (pad PAD_91): Pin mem_addr[3] of type output uses SSTL-2 Class I I/O standard
   Info: Location V6 (pad PAD_92): Pin mem_addr[4] of type output uses SSTL-2 Class I I/O standard
   Info: Location V5 (pad PAD_93): Pin mem_dm[0] of type output uses SSTL-2 Class I I/O standard
   Info: Location U7 (pad PAD_94): Pin mem_addr[5] of type output uses SSTL-2 Class I I/O standard
   Info: Location U8 (pad PAD_95): Pin mem_addr[6] of type output uses SSTL-2 Class I I/O standard
   Info: Location R11 (pad PAD_97): Pin mem_addr[7] of type output uses SSTL-2 Class I I/O standard
   Info: Location R12 (pad PAD_98): Pin mem_addr[8] of type output uses SSTL-2 Class I I/O standard
   Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
    Info: Location R9 (pad PAD_88): Pin mem_addr[0] of type output uses SSTL-2 Class I I/O standard
    Info: Location T8 (pad PAD_89): Pin mem_addr[1] of type output uses SSTL-2 Class I I/O standard
    Info: Location R10 (pad PAD_90): Pin mem_addr[2] of type output uses SSTL-2 Class I I/O standard
    Info: Location T9 (pad PAD_91): Pin mem_addr[3] of type output uses SSTL-2 Class I I/O standard
    Info: Location V6 (pad PAD_92): Pin mem_addr[4] of type output uses SSTL-2 Class I I/O standard
    Info: Location V5 (pad PAD_93): Pin mem_dm[0] of type output uses SSTL-2 Class I I/O standard
    Info: Location U7 (pad PAD_94): Pin mem_addr[5] of type output uses SSTL-2 Class I I/O standard
    Info: Location U8 (pad PAD_95): Pin mem_addr[6] of type output uses SSTL-2 Class I I/O standard
    Info: Location Y4 (pad PAD_96): unused
    Info: Location R11 (pad PAD_97): Pin mem_addr[7] of type output uses SSTL-2 Class I I/O standard
    Info: Location R12 (pad PAD_98): Pin mem_addr[8] of type output uses SSTL-2 Class I I/O standard
    Info: Location Y3 (pad PAD_99): unused
Error: Can't place pin mem_dq[1] to location W6
Error: Can't place VREF pin Y4 (VREFGROUP_B3_N1) for pin mem_dq[1] of type bi-directional with SSTL-2 Class I I/O standard at location W6
  Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 3 when the VREF pin Y4 (VREFGROUP_B3_N1) is used on device EP3C16F484C6 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
   Info: Location R9 (pad PAD_88): Pin mem_addr[0] of type output uses SSTL-2 Class I I/O standard
   Info: Location T8 (pad PAD_89): Pin mem_addr[1] of type output uses SSTL-2 Class I I/O standard
   Info: Location R10 (pad PAD_90): Pin mem_addr[2] of type output uses SSTL-2 Class I I/O standard
   Info: Location T9 (pad PAD_91): Pin mem_addr[3] of type output uses SSTL-2 Class I I/O standard
   Info: Location V6 (pad PAD_92): Pin mem_addr[4] of type output uses SSTL-2 Class I I/O standard
   Info: Location V5 (pad PAD_93): Pin mem_dm[0] of type output uses SSTL-2 Class I I/O standard
   Info: Location U7 (pad PAD_94): Pin mem_addr[5] of type output uses SSTL-2 Class I I/O standard
   Info: Location U8 (pad PAD_95): Pin mem_addr[6] of type output uses SSTL-2 Class I I/O standard
   Info: Location R11 (pad PAD_97): Pin mem_addr[7] of type output uses SSTL-2 Class I I/O standard
   Info: Location R12 (pad PAD_98): Pin mem_addr[8] of type output uses SSTL-2 Class I I/O standard
   Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
    Info: Location R9 (pad PAD_88): Pin mem_addr[0] of type output uses SSTL-2 Class I I/O standard
    Info: Location T8 (pad PAD_89): Pin mem_addr[1] of type output uses SSTL-2 Class I I/O standard
    Info: Location R10 (pad PAD_90): Pin mem_addr[2] of type output uses SSTL-2 Class I I/O standard
    Info: Location T9 (pad PAD_91): Pin mem_addr[3] of type output uses SSTL-2 Class I I/O standard
    Info: Location V6 (pad PAD_92): Pin mem_addr[4] of type output uses SSTL-2 Class I I/O standard
    Info: Location V5 (pad PAD_93): Pin mem_dm[0] of type output uses SSTL-2 Class I I/O standard
    Info: Location U7 (pad PAD_94): Pin mem_addr[5] of type output uses SSTL-2 Class I I/O standard
    Info: Location U8 (pad PAD_95): Pin mem_addr[6] of type output uses SSTL-2 Class I I/O standard
    Info: Location Y4 (pad PAD_96): unused
    Info: Location R11 (pad PAD_97): Pin mem_addr[7] of type output uses SSTL-2 Class I I/O standard
    Info: Location R12 (pad PAD_98): Pin mem_addr[8] of type output uses SSTL-2 Class I I/O standard
    Info: Location Y3 (pad PAD_99): unused
Error: Can't place pin mem_dq[2] to location AA4
Error: Can't place VREF pin Y4 (VREFGROUP_B3_N1) for pin mem_dq[2] of type bi-directional with SSTL-2 Class I I/O standard at location AA4
  Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 3 when the VREF pin Y4 (VREFGROUP_B3_N1) is used on device EP3C16F484C6 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
   Info: Location R9 (pad PAD_88): Pin mem_addr[0] of type output uses SSTL-2 Class I I/O standard
   Info: Location T8 (pad PAD_89): Pin mem_addr[1] of type output uses SSTL-2 Class I I/O standard
   Info: Location R10 (pad PAD_90): Pin mem_addr[2] of type output uses SSTL-2 Class I I/O standard
   Info: Location T9 (pad PAD_91): Pin mem_addr[3] of type output uses SSTL-2 Class I I/O standard
   Info: Location V6 (pad PAD_92): Pin mem_addr[4] of type output uses SSTL-2 Class I I/O standard
   Info: Location V5 (pad PAD_93): Pin mem_dm[0] of type output uses SSTL-2 Class I I/O standard
   Info: Location U7 (pad PAD_94): Pin mem_addr[5] of type output uses SSTL-2 Class I I/O standard
   Info: Location U8 (pad PAD_95): Pin mem_addr[6] of type output uses SSTL-2 Class I I/O standard
   Info: Location R11 (pad PAD_97): Pin mem_addr[7] of type output uses SSTL-2 Class I I/O standard
   Info: Location R12 (pad PAD_98): Pin mem_addr[8] of type output uses SSTL-2 Class I I/O standard
   Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
    Info: Location R9 (pad PAD_88): Pin mem_addr[0] of type output uses SSTL-2 Class I I/O standard
    Info: Location T8 (pad PAD_89): Pin mem_addr[1] of type output uses SSTL-2 Class I I/O standard
    Info: Location R10 (pad PAD_90): Pin mem_addr[2] of type output uses SSTL-2 Class I I/O standard
    Info: Location T9 (pad PAD_91): Pin mem_addr[3] of type output uses SSTL-2 Class I I/O standard
    Info: Location V6 (pad PAD_92): Pin mem_addr[4] of type output uses SSTL-2 Class I I/O standard
    Info: Location V5 (pad PAD_93): Pin mem_dm[0] of type output uses SSTL-2 Class I I/O standard
    Info: Location U7 (pad PAD_94): Pin mem_addr[5] of type output uses SSTL-2 Class I I/O standard
    Info: Location U8 (pad PAD_95): Pin mem_addr[6] of type output uses SSTL-2 Class I I/O standard
    Info: Location Y4 (pad PAD_96): unused
    Info: Location R11 (pad PAD_97): Pin mem_addr[7] of type output uses SSTL-2 Class I I/O standard
    Info: Location R12 (pad PAD_98): Pin mem_addr[8] of type output uses SSTL-2 Class I I/O standard
    Info: Location Y3 (pad PAD_99): unused
Error: Can't place pin mem_dq[3] to location AA5
Error: Can't place VREF pin Y4 (VREFGROUP_B3_N1) for pin mem_dq[3] of type bi-directional with SSTL-2 Class I I/O standard at location AA5
  Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 3 when the VREF pin Y4 (VREFGROUP_B3_N1) is used on device EP3C16F484C6 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
   Info: Location R9 (pad PAD_88): Pin mem_addr[0] of type output uses SSTL-2 Class I I/O standard
   Info: Location T8 (pad PAD_89): Pin mem_addr[1] of type output uses SSTL-2 Class I I/O standard
   Info: Location R10 (pad PAD_90): Pin mem_addr[2] of type output uses SSTL-2 Class I I/O standard
   Info: Location T9 (pad PAD_91): Pin mem_addr[3] of type output uses SSTL-2 Class I I/O standard
   Info: Location V6 (pad PAD_92): Pin mem_addr[4] of type output uses SSTL-2 Class I I/O standard
   Info: Location V5 (pad PAD_93): Pin mem_dm[0] of type output uses SSTL-2 Class I I/O standard
   Info: Location U7 (pad PAD_94): Pin mem_addr[5] of type output uses SSTL-2 Class I I/O standard
   Info: Location U8 (pad PAD_95): Pin mem_addr[6] of type output uses SSTL-2 Class I I/O standard
   Info: Location R11 (pad PAD_97): Pin mem_addr[7] of type output uses SSTL-2 Class I I/O standard
   Info: Location R12 (pad PAD_98): Pin mem_addr[8] of type output uses SSTL-2 Class I I/O standard
   Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
    Info: Location R9 (pad PAD_88): Pin mem_addr[0] of type output uses SSTL-2 Class I I/O standard
    Info: Location T8 (pad PAD_89): Pin mem_addr[1] of type output uses SSTL-2 Class I I/O standard
    Info: Location R10 (pad PAD_90): Pin mem_addr[2] of type output uses SSTL-2 Class I I/O standard
    Info: Location T9 (pad PAD_91): Pin mem_addr[3] of type output uses SSTL-2 Class I I/O standard
    Info: Location V6 (pad PAD_92): Pin mem_addr[4] of type output uses SSTL-2 Class I I/O standard
    Info: Location V5 (pad PAD_93): Pin mem_dm[0] of type output uses SSTL-2 Class I I/O standard
    Info: Location U7 (pad PAD_94): Pin mem_addr[5] of type output uses SSTL-2 Class I I/O standard
    Info: Location U8 (pad PAD_95): Pin mem_addr[6] of type output uses SSTL-2 Class I I/O standard
    Info: Location Y4 (pad PAD_96): unused
    Info: Location R11 (pad PAD_97): Pin mem_addr[7] of type output uses SSTL-2 Class I I/O standard
    Info: Location R12 (pad PAD_98): Pin mem_addr[8] of type output uses SSTL-2 Class I I/O standard
    Info: Location Y3 (pad PAD_99): unused
Error: Can't place pin mem_dq[4] to location W7
Error: Can't place VREF pin Y4 (VREFGROUP_B3_N1) for pin mem_dq[4] of type bi-directional with SSTL-2 Class I I/O standard at location W7
  Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 3 when the VREF pin Y4 (VREFGROUP_B3_N1) is used on device EP3C16F484C6 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
   Info: Location R9 (pad PAD_88): Pin mem_addr[0] of type output uses SSTL-2 Class I I/O standard
   Info: Location T8 (pad PAD_89): Pin mem_addr[1] of type output uses SSTL-2 Class I I/O standard
   Info: Location R10 (pad PAD_90): Pin mem_addr[2] of type output uses SSTL-2 Class I I/O standard
   Info: Location T9 (pad PAD_91): Pin mem_addr[3] of type output uses SSTL-2 Class I I/O standard
   Info: Location V6 (pad PAD_92): Pin mem_addr[4] of type output uses SSTL-2 Class I I/O standard
   Info: Location V5 (pad PAD_93): Pin mem_dm[0] of type output uses SSTL-2 Class I I/O standard
   Info: Location U7 (pad PAD_94): Pin mem_addr[5] of type output uses SSTL-2 Class I I/O standard
   Info: Location U8 (pad PAD_95): Pin mem_addr[6] of type output uses SSTL-2 Class I I/O standard
   Info: Location R11 (pad PAD_97): Pin mem_addr[7] of type output uses SSTL-2 Class I I/O standard
   Info: Location R12 (pad PAD_98): Pin mem_addr[8] of type output uses SSTL-2 Class I I/O standard
   Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
    Info: Location R9 (pad PAD_88): Pin mem_addr[0] of type output uses SSTL-2 Class I I/O standard
    Info: Location T8 (pad PAD_89): Pin mem_addr[1] of type output uses SSTL-2 Class I I/O standard
    Info: Location R10 (pad PAD_90): Pin mem_addr[2] of type output uses SSTL-2 Class I I/O standard
    Info: Location T9 (pad PAD_91): Pin mem_addr[3] of type output uses SSTL-2 Class I I/O standard
    Info: Location V6 (pad PAD_92): Pin mem_addr[4] of type output uses SSTL-2 Class I I/O standard
    Info: Location V5 (pad PAD_93): Pin mem_dm[0] of type output uses SSTL-2 Class I I/O standard
    Info: Location U7 (pad PAD_94): Pin mem_addr[5] of type output uses SSTL-2 Class I I/O standard
    Info: Location U8 (pad PAD_95): Pin mem_addr[6] of type output uses SSTL-2 Class I I/O standard
    Info: Location Y4 (pad PAD_96): unused
    Info: Location R11 (pad PAD_97): Pin mem_addr[7] of type output uses SSTL-2 Class I I/O standard
    Info: Location R12 (pad PAD_98): Pin mem_addr[8] of type output uses SSTL-2 Class I I/O standard
    Info: Location Y3 (pad PAD_99): unused
Error: Can't place pin mem_dq[15] to location W10
Error: Can't place VREF pin V9 (VREFGROUP_B3_N0) for pin mem_dq[15] of type bi-directional with SSTL-2 Class I I/O standard at location W10
  Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 3 when the VREF pin V9 (VREFGROUP_B3_N0) is used on device EP3C16F484C6 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
   Info: Location T10 (pad PAD_121): Pin mem_ba[0] of type output uses SSTL-2 Class I I/O standard
   Info: Location T11 (pad PAD_125): Pin mem_ba[1] of type output uses SSTL-2 Class I I/O standard
   Info: Location U11 (pad PAD_128): Pin mem_ras_n of type output uses SSTL-2 Class I I/O standard
   Info: Location Y10 (pad PAD_131): Pin mem_cke[0] of type output uses SSTL-2 Class I I/O standard
   Info: Location AA10 (pad PAD_132): Pin mem_cas_n of type output uses SSTL-2 Class I I/O standard
   Info: Following 1 pins have the same output enable group -12: 1 pins require VREF pin and 1 pins could be output
    Info: Location U10 (pad PAD_122): Pin mem_dq[10] of type bi-directional uses SSTL-2 Class I I/O standard
   Info: Following 1 pins have the same output enable group -13: 1 pins require VREF pin and 1 pins could be output
    Info: Location AA8 (pad PAD_123): Pin mem_dq[11] of type bi-directional uses SSTL-2 Class I I/O standard
   Info: Following 1 pins have the same output enable group -14: 1 pins require VREF pin and 1 pins could be output
    Info: Location AB8 (pad PAD_124): Pin mem_dq[12] of type bi-directional uses SSTL-2 Class I I/O standard
   Info: Following 1 pins have the same output enable group -15: 1 pins require VREF pin and 1 pins could be output
    Info: Location AA9 (pad PAD_126): Pin mem_dq[13] of type bi-directional uses SSTL-2 Class I I/O standard
   Info: Following 1 pins have the same output enable group -16: 1 pins require VREF pin and 1 pins could be output
    Info: Location V11 (pad PAD_129): Pin mem_dq[14] of type bi-directional uses SSTL-2 Class I I/O standard
   Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
    Info: Location T10 (pad PAD_121): Pin mem_ba[0] of type output uses SSTL-2 Class I I/O standard
    Info: Location U10 (pad PAD_122): Pin mem_dq[10] of type bi-directional uses SSTL-2 Class I I/O standard
    Info: Location AA8 (pad PAD_123): Pin mem_dq[11] of type bi-directional uses SSTL-2 Class I I/O standard
    Info: Location AB8 (pad PAD_124): Pin mem_dq[12] of type bi-directional uses SSTL-2 Class I I/O standard
    Info: Location T11 (pad PAD_125): Pin mem_ba[1] of type output uses SSTL-2 Class I I/O standard
    Info: Location AA9 (pad PAD_126): Pin mem_dq[13] of type bi-directional uses SSTL-2 Class I I/O standard
    Info: Location AB9 (pad PAD_127): unused
    Info: Location U11 (pad PAD_128): Pin mem_ras_n of type output uses SSTL-2 Class I I/O standard
    Info: Location V11 (pad PAD_129): Pin mem_dq[14] of type bi-directional uses SSTL-2 Class I I/O standard
    Info: Location W10 (pad PAD_130): unused
    Info: Location Y10 (pad PAD_131): Pin mem_cke[0] of type output uses SSTL-2 Class I I/O standard
    Info: Location AA10 (pad PAD_132): Pin mem_cas_n of type output uses SSTL-2 Class I I/O standard
Error: Can't place pin mem_dqs[1] to location AB9
Error: Can't place VREF pin V9 (VREFGROUP_B3_N0) for pin mem_dqs[1] of type bi-directional with SSTL-2 Class I I/O standard at location AB9
  Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 3 when the VREF pin V9 (VREFGROUP_B3_N0) is used on device EP3C16F484C6 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
   Info: Location T10 (pad PAD_121): Pin mem_ba[0] of type output uses SSTL-2 Class I I/O standard
   Info: Location T11 (pad PAD_125): Pin mem_ba[1] of type output uses SSTL-2 Class I I/O standard
   Info: Location U11 (pad PAD_128): Pin mem_ras_n of type output uses SSTL-2 Class I I/O standard
   Info: Location Y10 (pad PAD_131): Pin mem_cke[0] of type output uses SSTL-2 Class I I/O standard
   Info: Following 1 pins have the same output enable group -18: 1 pins require VREF pin and 1 pins could be output
    Info: Location V10 (pad PAD_120): Pin mem_dqs[0] of type bi-directional uses SSTL-2 Class I I/O standard
   Info: Following 1 pins have the same output enable group -12: 1 pins require VREF pin and 1 pins could be output
    Info: Location U10 (pad PAD_122): Pin mem_dq[10] of type bi-directional uses SSTL-2 Class I I/O standard
   Info: Following 1 pins have the same output enable group -13: 1 pins require VREF pin and 1 pins could be output
    Info: Location AA8 (pad PAD_123): Pin mem_dq[11] of type bi-directional uses SSTL-2 Class I I/O standard
   Info: Following 1 pins have the same output enable group -14: 1 pins require VREF pin and 1 pins could be output
    Info: Location AB8 (pad PAD_124): Pin mem_dq[12] of type bi-directional uses SSTL-2 Class I I/O standard
   Info: Following 1 pins have the same output enable group -15: 1 pins require VREF pin and 1 pins could be output
    Info: Location AA9 (pad PAD_126): Pin mem_dq[13] of type bi-directional uses SSTL-2 Class I I/O standard
   Info: Following 1 pins have the same output enable group -16: 1 pins require VREF pin and 1 pins could be output
    Info: Location V11 (pad PAD_129): Pin mem_dq[14] of type bi-directional uses SSTL-2 Class I I/O standard
   Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
    Info: Location V10 (pad PAD_120): Pin mem_dqs[0] of type bi-directional uses SSTL-2 Class I I/O standard
    Info: Location T10 (pad PAD_121): Pin mem_ba[0] of type output uses SSTL-2 Class I I/O standard
    Info: Location U10 (pad PAD_122): Pin mem_dq[10] of type bi-directional uses SSTL-2 Class I I/O standard
    Info: Location AA8 (pad PAD_123): Pin mem_dq[11] of type bi-directional uses SSTL-2 Class I I/O standard
    Info: Location AB8 (pad PAD_124): Pin mem_dq[12] of type bi-directional uses SSTL-2 Class I I/O standard
    Info: Location T11 (pad PAD_125): Pin mem_ba[1] of type output uses SSTL-2 Class I I/O standard
    Info: Location AA9 (pad PAD_126): Pin mem_dq[13] of type bi-directional uses SSTL-2 Class I I/O standard
    Info: Location AB9 (pad PAD_127): unused
    Info: Location U11 (pad PAD_128): Pin mem_ras_n of type output uses SSTL-2 Class I I/O standard
    Info: Location V11 (pad PAD_129): Pin mem_dq[14] of type bi-directional uses SSTL-2 Class I I/O standard
    Info: Location W10 (pad PAD_130): unused
    Info: Location Y10 (pad PAD_131): Pin mem_cke[0] of type output uses SSTL-2 Class I I/O standard
Error: Can't fit design in device
Error: Quartus II Fitter was unsuccessful. 28 errors, 3 warnings
Error: Peak virtual memory: 203 megabytes
Error: Processing ended: Tue Mar 27 16:02:18 2012
Error: Elapsed time: 00:00:06
Error: Total CPU time (on all processors): 00:00:05
Error: Quartus II Full Compilation was unsuccessful. 30 errors, 72 warnings

digitalimage

你这个要看芯片资料，dram管脚不是乱分配的，每一个group要在一个bank里面，而且也不是每个bank都可以分配给dram管脚用。仔细看一下资料，有详细说明的。

wangyingwei

同意楼上，是布线管脚的选择问题
DDR的布线中习惯把信号分成若干组来进行设计，分成同组的信号具有相关或者相似的信号特性。
    数据组： 对主板X8 DDR内存来说数据每8位（也就是一个byte）为一组可以分为八组，数据dq[0:7]、数据掩码dqm0、数据选通差分信号dqsp0 和dqsn0为一组
你要参考那个管脚手册和上面的原则来分配管脚

headforever

胡说八道！
这个问题实际上就是输出引脚分配问题。

tiangua

前面几个错误应该是差分对放置错误，差分对有两种，inout和out，看一下clk放的地方对不对。
同一个vcciobank里面相同方向的信号太多。没有保留vref引脚。

guoyu

每个Bank同时使用的DDIO有限制。

lionard

Thanks a lot!