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[招聘] 知名企业招聘IC设计和验证工程师-成都

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发表于 2012-3-25 11:16:49 | 显示全部楼层 |阅读模式

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本帖最后由 haha981604 于 2012-3-31 22:17 编辑

工作主要是CPU、DSP及多核Soc系统数字逻辑开发和验证,在业界也是非常有挑战的
。目前主要考虑数字IC方面的工程师职位,后续可能有编译器,IDE和core微架构等
职位开放。
以下是研发部招聘的职位,有兴趣的兄弟姐妹可以来凑凑热闹....
1. Digital IC Design Engineer
JOB DESCRIPTION:
- Micro-architecture definition/writing IC design spec.
- RTL coding for logic modules.
- Simulation/Verification of functionalities at both module level and top
level.
- Do module level synthesis / timing analysis
- Writing complete design/verification reports
- Silicon debug of the related module functionalities
- Writing test patterns for production tests
QUALIFICATION:
- BSEE with minimum 1-year or MSEE with minimum 1-year experience of
digital design experience
- Experience on SERDES is preferred.
- Relevant experience in high-speed digital design (Semi-flow: customer
layout + ASIC flow) is must
- Relevant experience in Cadence ICMS/ICFB design environment is must
- Solid knowledge of digital design building blocks (eg. Data-path,
Synchronizer, FIFO...)
- Strong skills of Verilog RTL coding and verification and debug.
- Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC,
PT, etc.
- Relevant experience in DDR/PCIE/USB/ETH interface design is a plus
- Self-motivated and team player

2. System Verification Engineer
JOB DESCRIPTION:
- Build system functional model based on technical specification or
product description and requirement with system verilog or systemC.
- Make test plan and write testbench to verify functionality and
performance of ASICS.
- Develop/maintain/enhance environment tools/scripts/make files.
QUALIFICATION:
- BSEE with minimum 1-year experience in ASIC verification.
- Good knowledge on (systemverilog or systemc) and verilog.
- Hands on experience with simulation and verification tools, such as NC,
Questasim/VCS.
- Proficiency in one of Specman E/Vera/SystemVerilog/SystemC verification
tools.
- Strong teamwork and communication ability.
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