Invited Paper--NANO ESD 2011

semico_ljj

Overview on the design of low-leakage power-rail
ESD clamp circuits in nanoscale CMOS processes

Invited Paper

Federico A. Altolaguirre and Ming-Dou Kery
Insitute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan.
yDept. of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan.

Abstract—The circuit techniques to overcome the gate leakage
issue in advanced nanoscale CMOS technologies are presented.
These circuit techniques can reduce the total leakage current
from the high value of 21A in the traditional power-rail
ESD clamp circuit down to only 96nA (under 1 Volt operating
voltage, at room temperature) while maintaining very high ESD
robustness (as high as 8kV HBM and 800V MM) in a 65-nm
CMOS technology.

wufuwei

good,thanks very much

kaluoota

谢谢楼主