Input offset simulation

forever1201 · 发表于 2012-2-23 16:16:52

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Does anyone know how to simulate " Input offset of clocked comparator " by Hspice ?

vint019 · 发表于 2012-2-23 21:49:03

1. Your comparator has gain stage and latch stage.
2. You can not see DC offset at latch stage, because it is saturated at VDD or GND.
3. Set your clock high to let the latch stage in driving mode. (clk=H, driving mode; clk=L, latch mode)
4. You do AC simulation to get voltage gain of your gain stage output.
5. You do DC simulation and do Monte-Carlo simulation. Short gain stage input to let zero input offset. Check gain stage output DC offset voltage for 3 sigma.
6. (output offset)/(voltage gain)=(input offset)
7. You do not worry "how about the offset of latch stage?". Your gain stage offset dominates total offset, because your gain stage voltage gain >20.

hoolish9 · 发表于 2012-2-27 06:15:13

very good

yu1004 · 发表于 2012-4-13 09:14:03

good！！！

s13571357 · 发表于 2013-2-3 21:23:59

不錯的訊息
謝謝分享

ccp106 · 发表于 2013-2-3 22:21:52

解释的很详细啊

jalong · 发表于 2014-2-25 08:39:27

不錯的資訊
感謝樓主分享

amplifier_bias · 发表于 2020-1-14 09:15:50

fightshan · 发表于 2020-5-6 15:34:27

vint019 发表于 2012-2-23 21:49
1. Your comparator has gain stage and latch stage.
2. You can not see DC offset at latch stage, beca ...

latch comparator的preamp都没有静态电流怎么仿真DC？AC？

[求助] Input offset simulation

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