请教MIPI的传输

yangweijlu

回复  gaojun927



我想请教一下，这个图是一个示意图，还是数据传输的真实时序图，就是说，来自DSI端 ...
atlandis 发表于 2012-2-23 14:12

                               
登录/注册后可看大图

  第一个问题描述的不清晰?  第二个问题,non burst mode就是在数据传输的时候,数据不是按照burst打包的而是一整行数据直接传输出去,这个要求controller有足够一行的缓冲ram空间;

MyRoger

回复 3# atlandis


   这是哪个技术文档的截图？谢谢！

111_ZH

直接用我们的MIPI CSI2 IP核就可。可以联系：sales@wwago-inc.com

目前，我们WWAGO公司的MIPI CSI2 的IP核，在业界处于领先位置。

我们的 CSI2 Tx (vs. other vendors)


We have a multiplexing CSI2 transmitter, which canmultiplex several data sources (e.g. 4 cameras) to a single CSI2 stream.Customers are forced to design a complex multiplexing means outside the IP core.


no other vendors have a multiplexing CSI2 transmitter.


我们的CSI2 Rx (vs. other vendors)


·   Our CSI2 Rx IP cores (inparticular the SVRPlus-CSI2) allow handling of several pixels per clock cycles;this enables the user to use slower clock frequencies


·    Our IP is the only oneto support 8-lane extended CSI2(目前全球，只有我们能提供支持8-lanes的CSI2 IP 核）


·   we are one of the only 2 IP cores with MIPI IOL certificate(全球通过 MIPI IOL认证的这个IP有2家，我们是其中一家)


---------------------------------
MIPI CSI2 Tx
1:  4-lane MIPI CSI2 transmitter for FPGA (SVT-CS4AP1-F )
key Functionality highlights include:  
- 1 clock lane, one to four data lanes(configurable)
- Simple interface – legacy parallel-video input, augmented by an Early-HD signal
- Supports RAW8, RAW10, RAW12, YUV420 (legacy, 8 bit, 10 bit), YUV422 (8 bit, 10 bit), and user-defined data formats
- Optionally supports all other pixel formats, with up to 16 bit per pixel (RAW14, RGB444, RGB555, RGB565) as defined in MIPI® CSI2.
- Uses simple off-FPGA analog PHY (clock and data lane modules)  
2:  4-lane MIPI CSI2 transmitter for ASIC (SVT-CS4AP1 )      
key Functionality highlights include:  
- 1 clock lane, up to four data lanes(configurable)
- Simple interface – legacy parallel-video input, augmented by an Early-HD signal
- Supports all pixel formats, with up to 16 bit per pixel - RGB444, RGB555, RGB565, RAW8, RAW10, RAW12, RAW14, YUV420 (legacy, 8 bit, 10 bit), YUV422 (8 bit, 10 bit), and user-defined data formats.
- Uses simple analog PHY (clock and data lane modules)
- Compact solution for image sensors

3:  Multiplexing 4-lane MIPI CSI2 transmitter  ( SVT-CS4AP2 )
key Functionality highlights include:  
- One clock lane, and one to 4 data lanes (configurable)
-  Up to 1.5 Gbps per lane
-  Supports CSI2 RAW8, RAW10, RAW12, all YUV420, all YUV422 and User-Defined 8-bit formats (other CSI2 standards available as an option)
-  Supports up to 8 concurrent video sources, for example, the sensor can send high resolution RAW12 image, where the first and last video lines contain blanking data, with embedded low  resolution preview data and with embedded JPEG data
- CRC and ECC generation
- Programmable timing parameters

MIPI CSI2 Rx
1:  Configurable 8-lane MIPI CSI2 Receiver for FPGA (SVRPlus-CSI2-F )
key Functionality highlights include:  
-  Configurable (register control) number of data lanes 1 to 4 or 1 to 8, according to  the state of the EIGHT_LANES compilation switch;
-  Configurable (register control) 1 or 2 clock lanes when the EIGHT_LANES  compilation switch is set to ON
-  64 bit internal data bus
- 1, 2 or 4 pixels output per clock, as set by the PARALLEL_PIXESL compilation switch
- Up to 1.5Gbps per lane
- All CSI2 functionality implemented in hardware, freeing the CPU to other tasks
- Support of all data formats
- Extensive set of registers, accessible by AMBA APB bus (or, optionally, by I2C)
- Programmable timing parameters
- Optional support of CSI2 compressed-video formats
- Optional output FIFO for continuous output streams
- Optional Error counting hardware, for on-line BER measurements

2:  Configurable 8-lane MIPI CSI2 Receiver for ASIC (SVRPlus-CSI2-I )
key Functionality highlights include:  
-  Configurable 1, 2, 3 or 4 data lanes (SVRPlus-CSI2-I-4X);
-  Configurable 1 or 2 clock lanes;  1,2,3,4 or 8 data lanes(SVRPlus-CSI2-I-8X)
-  64 bit internal data bus for high throughput
-  1, 2  or 4 Parallel pixels  output per clock
-  Up to 1.5Gbps per lane
-  All CSI2 functionality implemented in hardware, freeing the CPU to other tasks
-  Support of all data formats
-  Rich set of registers, allowing tracking of all kinds of communication errors
-  Programmable timing parameters
-  AMBA-APB control of all registers (I2C control optional)
-  All DPHY features, except for the analog front  end ,implemented by RTL
-  Optional support of CSI2 compressed  video formats
- Optional output FIFO for continuous output streams
- Optional Error counting , to  allow on-line BER measurements


有兴趣可以联系：sales@wwago-inc.com

浪海

MIPI 只要是HS和LP两个模式。HS模式先是250Mv的差分时钟。LP模式先是1.2v时钟。很多的设计中只有HS模式，让高速时钟一直在工作。不进入LP模式时钟