IEEE－A Stabilization Technique for PhaseLocked Frequency Synthesizers（2003）

semico_ljj

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 6, JUNE 2003

A Stabilization Technique for PhaseLocked Frequency Synthesizers

by
Tai-Cheng Lee and Behzad Razavi, Fellow, IEEE

Abstract
  A stabilization technique is presented that relaxes the
tradeoff between the settling speed and the magnitude of output
sidebands in phase-locked frequency synthesizers. The method introduces
a zero in the open-loop transfer function through the use
of a discrete-time delay cell, obviating the need for resistors in
the loop filter. A 2.4-GHz CMOS frequency synthesizer employing
the technique settles in approximately 60 s with 1-MHz channel
spacing while exhibiting a sideband magnitude of 58.7 dBc. Designed
for Bluetooth applications and fabricated in a 0.25- m digital
CMOS technology, the synthesizer achieves a phase noise of
112 dBc/Hz at 1-MHz offset and consumes 20 mW from a 2.5-V
supply.

Index Terms
  Charge pumps, feedforward, loop stability, oscillators,
phase-locked loops (PLLs), prescalers, synthesizers.

fds

Thanks

ahuic

很不错啊
好东西

gdy

Nice one

StateoftheArt

你这么多钱可否贡献给辛苦的同学们

   

原帖由 semico_ljj 于 2006-11-23 09:26 发表
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 6, JUNE 2003

A Stabilization Technique for PhaseLocked Frequency Synthesizers

by
Tai-Cheng Lee and Behzad Razavi, Fellow, IEEE

Abstr ...

longwugdnt

Nice,

longwugdnt

你这么多钱可否贡献给辛苦的同学们

StateoftheArt

下起来才知道钱太少

   

原帖由 longwugdnt 于 2006-11-23 19:39 发表
你这么多钱可否贡献给辛苦的同学们

lougx1207

谢了，楼主

骑着蜗牛追火箭

不错，，，谢谢。。