|
|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 6, JUNE 2003
A Stabilization Technique for PhaseLocked Frequency Synthesizers
by
Tai-Cheng Lee and Behzad Razavi, Fellow, IEEE
Abstract
A stabilization technique is presented that relaxes the
tradeoff between the settling speed and the magnitude of output
sidebands in phase-locked frequency synthesizers. The method introduces
a zero in the open-loop transfer function through the use
of a discrete-time delay cell, obviating the need for resistors in
the loop filter. A 2.4-GHz CMOS frequency synthesizer employing
the technique settles in approximately 60 s with 1-MHz channel
spacing while exhibiting a sideband magnitude of 58.7 dBc. Designed
for Bluetooth applications and fabricated in a 0.25- m digital
CMOS technology, the synthesizer achieves a phase noise of
112 dBc/Hz at 1-MHz offset and consumes 20 mW from a 2.5-V
supply.
Index Terms
Charge pumps, feedforward, loop stability, oscillators,
phase-locked loops (PLLs), prescalers, synthesizers. |
|
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2006-11-23 09:26:48
你这么多钱可否贡献给辛苦的同学们