IEEE--A75mW128MHz CDMA Baseband Demodulator HighSpeed WirelessApplications

semico_ljj

A 75mW 128MHz DS-CDMA Baseband Demodulator for HighSpeed Wireless Applications
by
Keith K. Onodera and Paul R. Gray, Fellow, IEEE

Abstract  
A DS-CDMA demodulator uses analog sampled-data
signal processing to achieve a 75-mW power dissipation and a
128-MS/s processing rate in a 1.2-m double-metal double-poly
CMOS process. To demodulate the signal, a low-power passive
correlation technique is introduced that eliminates the integrating
opamp with its associated power and settling time overhead. In
a prototype demodulator, six 64-chip correlators recover the 2-
Mb/s data stream from the doubly modulated [pseudorandom
noise (PN) and Walsh] quadrature input signal. An on-chip 10-b
pipelined ADC sampling at 8 MS/s follows the analog correlation
to permit digital implementation of the acquisition and tracking
algorithms.
Index Terms—CMOS analog integrated circuits, code division
multiaccess, correlators, direct sequence spread spectrum, passive
circuits, passive correlator, pseudonoise coded communication,
sampled data filters, spread spectrum communication, switched
capacitor circuits, wireless LAN.

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