职业机会 Physical design engineer 知名美资企业

猎头Jennifer

Job Title： Physical Design Engineer

Main Responsibilities：

1.
Implements IC design with emphasis on backend tasks, including floor-planning, CTS, P&R, power optimization, power/signal integrity.

2.
Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).

3.
Responsible for Die size estimation, floor-planning, power planning and power analysis.

4.
Static Timing analysis (Prime Time) and timing fix.

5.
Candidate must be a team player with excellent verbal and written communication skills, strong project management capabilities, and be able to successfully drive a project to completion.

Job Requirements：

1.   5 or more years of hands-on experience in IC physical design, verification and tapeouts.

2.   Strong background of deep sub-micron CMOS IC physical design including Floor planning, P&R, CTS, IR Drop Analysis, extraction, timing closure with Signal Integrity.

3.   Proven track records of leading tapeouts with at least one use low-power methodology having multi-VDD or switchable voltage-domains.

4.   Experience with scripting languages (Perl, TCL, or Shell) to make reusable automatically flow .

5.   Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler / SOC-Encounter/ Milky-way/ Star-RCX) is a plus.

6.   Experience and knowledge about custom layout is a plus.

7.   Experience and knowledge about DFT is a plus.

8.   Good analytical and debugging skills.

9.   Good command of English.

如对此职位感兴趣可加MSN:jennifer_wxx@msn.cn 了解联系情况，

或发送邮件至：job606@green-information.com

   

猎头Jennifer

Job Title： Physical Design Engineer

Main Responsibilities：
1.Implements IC design with emphasis on backend tasks, including floor-planning, CTS, P&R, power optimization, power/signal integrity.
2.Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).
3.Responsible for Die size estimation, floor-planning, power planning and power analysis.
4.Static Timing analysis (Prime Time) and timing fix.
5.Candidate must be a team player with excellent verbal and written communication skills, strong project management capabilities, and be able to successfully drive a project to completion.

Job Requirements：

1.5 or more years of hands-on experience in IC physical design, verification and tapeouts.
2.Strong background of deep sub-micron CMOS IC physical design including Floor planning, P&R, CTS, IR Drop Analysis, extraction, timing closure with Signal Integrity.
3. Proven track records of leading tapeouts with at least one use low-power methodology having multi-VDD or switchable voltage-domains.
4.Experience with scripting languages (Perl, TCL, or Shell) to make reusable automatically flow .
5.Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler / SOC-Encounter/ Milky-way/ Star-RCX) is a plus.
6.Experience and knowledge about custom layout is a plus.
7.Experience and knowledge about DFT is a plus.
8.Good analytical and debugging skills.
9.Good command of English.




如对此职位感兴趣可加MSN:jennifer_wxx@msn.cn 了解联系情况，

或发送邮件至：job606@green-information.com

yajunjakey

你发错地方了

devop

大家觉得这个职位一般薪水应该是多少啊？
职位描述有没有太泛泛呢

icfbicfb

哪家么，现在招后端的单位这么多

zhoufly1234

哪家公司啊？