请教高手一个综合报错的问题！谢谢

cuihaolin

报的错误是：

Error: Required argument '-name' was not found (CMD-007)

Error: Required argument '-name' was not found (CMD-007)

Error: Required argument 'port_list' was not found (CMD-007)

Error: Required argument 'port_pin_list' was not found (CMD-007)

脚本如下：

#_________________________________________________

#set up path and library

set search_path
[list /home/hlcui/lib_path]

set target_library [list fs90a_c_sc_wc.db]

set link_library
[list {*} fs90a_c_sc_wc.db fs90a_c_sc_bc.db]

set symbol_library [list fs90a_c_sc.sdb]

#_______________________________________________

#design entry

analyze -format verilog des_ctrl.v

analyze -format verilog des_cal.v

analyze -format verilog des_top.v

elaborate des_top

current_design des_top

uniquify

check_design

#________________________________________________

set_wire_load_model large_wl

set_wire_load_model enclosed

set_operating_conditions WCCOM

create_clock -period 33 -waveform [list 0 16.5] clock

set_clock_latency 2.0 [get_clocks clock]

set_clock_uncertainty -setup 1.0 [get_clocks clock]

set_dont_touch_network [list clock rst]

#_________________________________________________

#input drives

set_driving_cell -lib_cell BUFFD2 -pin Z

set_drive 0 [list clock rst]

#_________________________________________________

#output load

set_load 1 [all_outputs]

#_________________________________________________

#set input & output delays

set_input_delay 10.0 -clock clock[all_inputs]

set_input_delay -max 25.0 -clock clock [all_inputs]

set_input_delay -min -2.0 -clock clock [all_inputs]

set_output_delay 10.0 -clock clock [all_outputs]

#___________________________________________________

#compile and write the database

compile

current_design des_top

write -hierarchy -output des_top.db

write -format verilog -hierarchy -output des_top.sv

#____________________________________________________

#current reports

report_timing -nworst 50