"ADC for high speed links" recent 博士论文 Stanford University

angelaboy

ANALOG-TO-DIGITAL CONVERTERS FOR HIGH-SPEED LINKS
A DISSERTATION
SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING
AND THE COMMITTEE ON GRADUATE STUDIES
OF STANFORD UNIVERSITY
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

albert_eetop

摘要中的一部分：We choose a single-slope ADC as a candidate for interleaving because
of its simplicity, linearity, low-power operation, small area, and small input
capacitance. This choice is nevertheless unusual because of single-slope's reputation
for long conversion time, normally taking 2Nbits time steps, where Nbits is the ADC
resolution. However, because PLLs and/or DLLs in high-speed links normally
generate very fine time steps, the conversion rates of single-slope ADCs for relatively
low resolution can be pushed to Gsps range. We demonstrate the suitability of singleslope
ADCs for high-speed low-power operation with a proof-of-concept design in the
high-speed 45nm TI CMOS technology. In simulation, the ADC was capable of 4.5bit
1.6Gsps or 5.5bit 0.8Gsps operation while consuming 3mW of power from a 1V
supply.
The prototype was, however, fabricated without redesign in a different,
low-leakage, variant of 45nm technology. Due to differences in device characteristics,
the chip operated at only 800MHz in a 4.5-bit mode and at 400MHz in a 5.5-bit mode
while consuming 4mW from a 1.2V supply. Nevertheless, it lays groundwork for
simple high-speed low-power ADCs based on a single-slope architecture.

ralphtw

ADC for high speed links

aqishisi

这份资料太有用了，谢谢分享

efong

thank you