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PMOS-Based Power-Rail ESD Clamp Circuit with
Adjustable Holding Voltage Controlled by ESD Detection
Circuit
Chih-Ting Yeh (1, 2), Yung-Chih Liang (2), and Ming-Dou Ker (1, 3）
(1) Department of Electronics Engineering & Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan
(2) Information and Communications Research Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan
(3) Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan
Abstract - A new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been
proposed and verified in a 65nm 1.2V CMOS process. The new proposed design with adjustable holding
voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced
latch-on event. The layout area and the standby leakage current of this new proposed design are much superior
to that of traditional RC-based power-rail ESD clamp circuit with NMOS as main ESD clamp device. |
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发表于 2011-10-5 21:06:49
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