2010－On-Chip ESD Detection Circuit for System-Level ESD－MD Ker

semico_ljj

On-Chip ESD Detection Circuit for System-Level ESD
Protection Design

Ming-Dou Ker 1, 2, Wan-Yen Lin1, Cheng-Cheng Yen1, Che-Ming Yang3, Tung-Yang Chen3,
and Shih-Fan Chen3

1 Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan
2 Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan
3 Research and Development Center, Himax Technologies, Inc., Tainan, Taiwan

Abstract
A new on-chip CR-based electrostatic discharge (ESD)
detection circuit for system-level ESD protection design
is proposed in this work. The circuit performance to
detect positive or negative electrical transients generated
by system-level ESD tests has been analyzed in HSPICE
simulation and verified in silicon chip. The experimental
results in a 0.13-m CMOS process have confirmed that
the proposed detection circuit can detect ESD-induced
transient disturbance during system-level ESD zapping.
The detection results can be used as system recovery
firmware index to improve the immunity of CMOS IC
products against system-level ESD stress.

semico_ljj

best。。。

qiang177

回复 1# semico_ljj


   谢谢！

mtwumtwu

good materila for ESD design

tingyc

谢谢！谢谢！

happywith123us

不错的东西

fancyher

多谢楼主

happywith123us

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雷叔叔

thanks

azen812

Thanks a lot
This is an very important issue