很多都是后端的知识点
Typical ASIC design flow .................................................................................................................2
时钟抖动 (Clock Jitter) ....................................................................................................................5
信号同步的窍门...............................................................................................................................8
数字后端流程..................................................................................................................................9
DC 概论之一 setup time 与 hold time .......................................................................................11
DC 概论二之fanout 与skew.........................................................................................................14
DC 概论三之setup time 与 hold time 之二................................................................................21
DC 概论四之setup time 与hold time 之三.................................................................................26
DC 概论五之high fanout...............................................................................................................42
DC 概论六之multicycle_path ......................................................................................................58
DC 概论七之gated clock...............................................................................................................75
DC 概论之IO 约束........................................................................................................................84
DC 优化约束.................................................................................................................................90
Synopsys Synthesis Constraints Template ......................................................................................92
功耗和门控时钟的的基本概念.....................................................................................................95
对FALSE PATH 的理解................................................................................................................97
TimeQuest 时钟分析....................................................................................................................101
静态时序分析...............................................................................................................................105
寄生参数提取和静态时序分析...................................................................................................124
IC 设计中的时钟类型约束..........................................................................................................130
IC 设计流程及工具......................................................................................................................132
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发表于 2011-10-11 14:39:22
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