VHDL attribute 问题

shufeng123 · 发表于 2011-9-15 17:26:15

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attribute DLL_FREQUENCY_MODE  : string;
attribute DLL_FREQUENCY_MODE  of LclkDcm : label is "HIGH";
-- attribute DLL_FREQUENCY_MODE  of SysDcm : label is "LOW" ;
attribute CLKOUT_PHASE_SHIFT  : string;
attribute CLKOUT_PHASE_SHIFT  of LclkDcm : label is "VARIABLE";
-- attribute CLKOUT_PHASE_SHIFT  of LclkDcm : label is "FIXED";
-- attribute CLKOUT_PHASE_SHIFT  of LclkDcm : label is "NONE";
attribute PHASE_SHIFT : string;
attribute PHASE_SHIFT       of LclkDcm : label is "-255";
-- attribute PHASE_SHIFT       of LclkDcm : label is "0";
attribute CLKDV_DIVIDE : string;
attribute CLKDV_DIVIDE       of LclkDcm : label is "3";
-- attribute CLKDV_DIVIDE       of SysDcm : label is "3" ;
attribute DUTY_CYCLE_CORRECTION : string;
attribute DUTY_CYCLE_CORRECTION of LclkDcm : label is "TRUE";
-- attribute DUTY_CYCLE_CORRECTION of SysDcm : label is "TRUE" ;
attribute DESKEW_ADJUST  : string;
attribute DESKEW_ADJUST       of LclkDcm : label is "SOURCE_SYNCHRONOUS";
-- attribute DESKEW_ADJUST       of SysDcm : label is "2" ;
attribute CLKIN_DIVIDE_BY_2  : string;
attribute CLKIN_DIVIDE_BY_2  of LclkDcm : label is "FALSE";
attribute RLOC_ORIGIN : string;

如果需把VHDL代码转换成verilog代码，VHDL属性怎么解决呀。请教。

icfbicfb · 发表于 2011-9-15 21:05:07

问下前端版面，

[求助] VHDL attribute 问题

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