On Behavioral Modeling for PLL Circuits with Non-Ideal Effects

hi_china59

On Behavioral Modeling for Phase-Locked Loop Circuits with Non-Ideal Effects
目录............................................................................................... i

第1 章 序论................................................................................. 1
1.1 研究动机....................................................................... 1
1.2 论文组织....................................................................... 6

第2 章 背景知识研读................................................................. 7
2.1 锁相回路(PLL)的原理.................................................. 7
2.1.1 系统架构介绍.......................................................................................7
2.1.2 相位频率侦测器(Phase Frequency Detector).....................................8
2.1.3 电荷充放器(Charge Pump) ...............................................................10
2.1.4 低通滤波器(Low Pass Filter)............................................................11
2.1.5 压控震荡器(Voltage Controlled Oscillator)......................................12
2.1.6 除频器(Frequency Divider) ] ............................................................13
2.2 理想Verilog-A 程序语言的PLL 模块介绍.............. 14
2.2.1 序论....................................................................................................14
2.2.2 相位频率侦测器(PFD)....................................................................14
2.2.3 电荷充放器与低通滤波器(CP_LPF) .............................................17
2.2.4 压控震荡器(VCO) ..........................................................................22
2.2.5 除频器(FD)......................................................................................25
2.2.6 实验模拟结果..................................................................................28
2.2.7 行为模拟结果讨论..........................................................................30
2.3 探讨其它行为模式建立扰动(Jitter)上的做法............ 32

第3 章 非理想PLL 的行为模式讨论.................................... 34
3.1 序论............................................................................. 34
3.2 非理想扰动(Jitter)的来源........................................... 35
3.3 电路非理想因素讨论与模拟结果............................. 36
3.3.1 实验种类的建立..............................................................................36
3.3.2 相位频率侦测器的非理想因素......................................................38
3.3.3 电荷充放器与低通滤波器(CP_LPF)的非理想因素.....................40
3.3.4 总体参数粹取流程说明................................................................42

第4 章 模拟结果与分析.......................................................... 44
4.1 实验一......................................................................... 44
4.1.1 Verilog-A 的模拟结果.....................................................................44
4.1.2 Hspice 的模拟结果.........................................................................45
4.1.3 模拟结果比较..................................................................................45
4.2 实验二......................................................................... 47
4.2.1 Verilog-A 的模拟结果.....................................................................47
4.2.2 Hspice 的模拟结果.........................................................................47
4.2.3 模拟结果比较..................................................................................48
4.3 Cadence 内建PLL 模块之仿真结果比较及讨论....... 49

第5 章 结论与未来工作.......................................................... 52
参考文献........................................................................................ 54

etopyes8

非常感谢

xinlianxin

看上去很好哦

bloodylord

很全的资料

原始逻辑

好东西！！

xuleiwx

是国立中央大学的研究生论文。

hnwulei

On Behavioral Modeling for PLL Circuits with Non-Ideal Effects

guoxiliang

好东西啊！

peterlin2010

是否跟這邊 2.2M byte 同個?
8F
http://bbs.eetop.cn/thread-115047-1-1.html

cdting

非常感謝~~~~