在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 3924|回复: 5

[求助] Analog design signoff checklist

[复制链接]
发表于 2011-8-24 15:29:13 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
Hello, can anybody share me analog design signoff checklist?

For example, in digital design, it will be

1. functional: test regression passing rate; coverage; etc...
2. Timing: STA; postsim; etc...
...

In analog field, in the real tape-out signoff flow, is there any similar checklist?

Thanks,
发表于 2011-8-25 15:41:47 | 显示全部楼层
it's something you should already know before you became a manager
 楼主| 发表于 2011-8-26 13:22:36 | 显示全部楼层
Can anybody share valuable experience here?

Thanks,
发表于 2011-8-26 14:07:21 | 显示全部楼层
It seems a decent question, and it will help people to follow the right process.

There are two many people who are willing to take short cut, and very few people want to follow the process.
发表于 2011-9-2 03:34:28 | 显示全部楼层
1. postsim at 5 corners and make sure there is some tolerance.
for example 300Mhz 10bit DAC spec, we have to postsim at  350Mhz or higher
 楼主| 发表于 2011-9-8 17:16:20 | 显示全部楼层
Thanks, hugodarwin.

How many testcases do you use for simulation? Only some little sequences which can be put in one test case?
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条

小黑屋| 手机版| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-11-5 16:24 , Processed in 0.023399 second(s), 9 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表