An efficient script-based RTL-to-GDSII flow

immonster

ABSTRACT
The integration of complex circuits on silicon has been known for long to require longer schedules than FPGA prototyping because of the complexity of silicon processes and the variations and inaccuracies to take into account. But with the most recent generation of physical implementation tools which ensure a better prediction and correlation between the successive design phases than before, it has now become feasible to integrate multi-million transistors circuits within an aggressive time frame.
This paper describes how Abilis Systems has achieved a short cycle-time project in a 130-nm technology for prototyping a multi-DSP architecture with several shared memories running at 100 MHz containing about 350k instances and more than 400KB of SRAMs, using tightly correlated physical design tools including Jupiter-XT, Physical Compiler, Astro and Star-RCXT. Starting from new technology design kit and libraries, a semi-automated flow including floor planning, physical synthesis routing and verification has allowed a 2-month physical implementation from RTL to GDSII ensuring comfortable correlations between design steps.
By applying a methodology and a flow already proved on other similar technologies and easily portable to other libraries, the use of scripts, of consistent timing engines and standard design exchange formats has consolidated a tight schedule.

IC狂人

thank you

fanjx

have a look

ssusheel444

回复 1# immonster


   thanks...............

zhangds

这小文档有用吗？