硕士论文 Design of CMOS DLL and Data Recovery Circuit

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Design of CMOS DLL and Data Recovery Circuit
台湾大学电子工程学研究所硕士论文，CMOS延迟锁定回路及资料回复电路之设计
Chapter 1 Introductions of the DLL and Data Recovery 1
1.1 Basics of the delay- locked Loops 1
1.1.1 Stability Analysis of the DLL system 3
1.2 Basics of the Clock-Data Recovery 4
1.2.1 NRZ data and PRBS signal 6
1.3 Reference 7

Chapter 2 The System Architecture 9
2.1 Introduction 9
2.2 Transmitter 10
2.2.1 Multiplexer 10
2.2.2 Delay locked loop 11
2.2.3 System Behavior simulation 12
2.3 Receiver 14
2.3.1 Clock Data Recover circuit 15
2.3.2 System Behavior simulation 16
2.4 Summary 19
2.5 Reference 19

Chapter 3 A WIDE-RANGE LOW-JITTER DELAY-LOCKED LOOP 21
3.1 Introduction 21
3.2 Wide Range Locked Problem and Solution’s Overview 22
3.3 Circuit Descriptions 24
3.3.1 Voltage Control Delay Line 24
3.3.2 Voltage Control Delay Cell 25
3.3.3 Phase Frequency Detector 26
3.3.4 Charge Pump 28
3.3.5 Phase Comparator 29
3.3.6 Loop Filter 30
3.3.7 Duty Cycle Corrector 31
3.4 Simulation Results 32
3.4.1 V o lt age control Delay Line 32
3.4.2 Phase Frequency Detector 34
3.4.3 All system of DLL 34
3.5 Experiment 37
3.5.1 E x p erimental setup 37
3.5.2 Print Circuit Board layout 38
3.5.3 Experimental results 39
3.6 Summary 44
3.7 Reference 45

Chapter 4 3.125Gbps Clock Data Recovery 47
4.1 Introduction 47
4.2 Circuit Descriptions 48
4.2.1 Voltage-controlled Oscillator 48
4.2.2 Delay Cell 49
4.2.3 Phase Detector 50
4.2.4 Charge Pump 51
4.2.5 Loop filter 52
4.2.6 Frequency Detector 54
4.2.7 Divider 55
4.2.8 Binary search circuit – SAR circuit 56
4.3 Simulation results 57
4.3.1 Voltage control Oscillator 57
4.3.2 Phase Detector and Charge Pump 60
4.3.3 Divider 61
4.3.4 System simulation 62
4.4 Summary 64
4.5 References 65

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