AMD-BJ"ASIC Design Engineer for SoC“

lotus6

AMD是一家专注于微处理器设计和生产的跨国公司，总部位于美国加州硅谷内森尼韦尔。AMD为电脑、通信及消费电子市场供应各种集成电路产品，其中包括中央处理器、图形处理器、闪存、芯片组以及其他半导体技术。
简历发送至：glen-china@qq.com
请在发送简历时按以下格式命名邮件标题（应聘岗位+姓名+现任职位），谢谢合作。
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Responsibility:
•        Participate in SOC IC project logic design
•        Working with architect to define chip level specification, including clock and power targets, IP selection, floorplan review etc.
•        Develop RTL code for chip level in Verilog HDL and make sure functional correct and reusable for different configuration.
•        Synthesis and deliver netlist that meeting timing, area and power requirement. Help PD on the floorplanning and close timing.
•        Work very closely with physical design engineers to help on floorplan, timing closure, power design validation and etc.
•        Bring-up ASIC. Guide hardware team to solve design problem in application. Help to short Time-To-Market.

Requirement:
•        MS degree of EE.  
•        Communicate effectively within a global business environment (must be proficient in both spoken and written English)
•        Experience in logic design, synthesis, static timing analysis.
•        Experience with ASIC EDA tools used in synthesis, simulation, static timing analysis, and formal verification
•        Familiar with unix/linux and scripts (tcl, perl etc.)
•        Excellent technical troubleshooting and demonstrated problem solving skills
•        Possesses specialized knowledge of  Computer architecture and computer arithmetic (a plus)
•        Possesses specialized knowledge of  Computer graphic knowledge (a plus)

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