急聘Staff Physical Design Engineer 上海

cavell2010

Staff Physical Design Engineer
Responsibilities:

Responsible for driving and executing the backend methodology from product inception through tapeout including block and chip-level floor planning, placement, scan-reordering, clock tree synthesis, in-place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs) and DRC/LVS/DFM checks.
Define and evolve backend low-power design methodology in 40nm technology to support aggressive low-power techniques for chips having multiple power-domains and dynamic voltage-scaling.
Automate, improve and maintain implementation methods making physical design cycle predictable and keep abreast with industry trends/tools and methodologies.
Integrate of Analog and RF-macros using their library models and closing timing at the interface level.
Provide technical direction, mentoring and enhance skills within the physical design team.
Interface with Design and Program Managers to define schedule, resource requirements and track backend schedule.


Qualifications:

Strong background of deep sub-micron CMOS IC physical design including Floor planning, P&R, CTS, IR Drop Analysis, extraction, timing closure with Signal Integrity.

Proven track records of leading multiple product tapeouts with at least one use low-power methodology having multi-VDD or switchable voltage-domains.

Vast experience identifying and resolving physical implementation issues related to Congestion, Routing & Timing Closure (including Crosstalk)

Hands on experience and detailed knowledge of Synopsys (preferred), Cadence or Magma Physical Design-tools.

Expertise in scripting languages like PERL, TCL, AWK, shell, etc. Must be a team player with excellent verbal and written communication skill.

8+ years of direct experience on physical design (MS 6+ years)

有意请联系：cavell2010@hotmail.com，谢谢！

ficai

从产业转移到角度看未来10年是中国ic研发的黄金时期，瓶颈在于人才缺乏；
所以大家加油啊，想赚的多就要学的多；

joemool

6+ years
...

还没毕业的MS路过