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发表于 2011-6-26 10:36:13
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本帖最后由 一目了然 于 2011-6-26 10:37 编辑
哎這論壇有bug,不小心發了兩次。
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我應該答不全,坐等牛人更好的答案。
Assume system VDD and clock frequency have been defined
reduce leakage:
1. transistor level: use high Vt cell or bias the body to level up Vt; reduce WlL.
2. circuit level: power gating, DVS
reduce dynamic:
1. transistor level: use high Vt cell or bias the body to level up Vt; reduce WlL(but be careful with the drive current)
2. circuit level: power gating, DVFS, use small cells(reduce CL)
3. system level: coding for less switching |
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