诚聘 ASIC Design Engineer

asic_tapeout

诚聘 asic Design Engineer

登录/注册后可看大图 美资公司LSI上海研发中心高薪诚聘通讯存储领域人才，薪水待遇优厚，今年开始配股了，部分人员有出国培训机会。(部门内部推荐,成功机会更高) 有意者请将中英文简历发送至：asic_tapeout@hotmail.com ASIC Design Engineer Job Description - LSI Corporation offers an excellent opportunity to contribute to a team environment and to grow personal career path. You will be working with internal and external customers to develop state of the art IC solutions utilizing LSI's leading edge CMOS cell-based ASIC technologies. You will have responsibility for ASIC designs through all of the key development and implementation phases including RTL analysis, synthesis, design optimization, timing verification, simulation, test insertion, physical design, vector generation, and post-prototype test support. Candidates will have opportunity to work on the latest 40nm/28nm designs. Detail design tasks include - Presales support (die size support, memory generation, addressing customer questions and concerns.) - RTL analysis & synthesis - Top level and block level physical design Implementation (bonding, floor planning, power structure insertion, place and route, timing closure) - Test structure insertion/silicon testing debug - Formal verification - Static timing analysis - Cross talk analysis - Power verification - Physical verification - Overtime, candidates are expected to develop the most of above skills. Candidates who have the desire to seek the in-depth and broad technical challenge should apply. Requirements/Qualifications (Education) Education: BS/MS Electrical, Computer Engineering or Equivalent - 2+ years experience in ASIC design and implementation. Familiar with all aspects of ASIC design implementation flow and specializing in physical design or DFT implementation. The ideal candidate should have successfully completed at least one mid-size ASIC or ASSP tapeout. - Experience with Synopsys Astro or ICC is a plus. Other physical design tool experience will also be considered. Scripting skill is a strong plus. - Experience in debugging prototypes considered a strong plus. Knowledge and hands on use of test insertion / vector generation / verification a plus. Some experience with Signal integrity a bonus. - Experience in working with customers is desired. Must possess excellent communication skills and strong self-motivation. Be able to effectively communicate with other members of the design team, supporting organizations, and management. This position requires frequent interface with LSI customers - Candidates have ONE OR MORE good skill sets of the following areas are highly encouraged to apply: - RTL Analysis/Synthesis/STA: The ideal candidate should have strong skills for the front-end of design - implementation which includes RTL Analysis, Synthesis Strategies, and STA setup for complex ASIC - environments. This would include strategies for power management. - OR - Physical Design Implementation: The ideal candidate should be strong in the Physical Design (at least at block level) which includes floor planning, design closure, & STA. Having strong DRC & LVS skills are a plus. Strong - Synopsys Astro/ICC experience a plus. Having Mentor Calibre skills a plus. - OR - Physical Verification: The ideal candidate should have in-depth understanding of transistor level IC fabrication process, familiar with major foundries(TSMC or SMIC) runsets and verification flow, custom layout experience is a plus, successfully done LVS/DRC/ERC/Antenna check for multiple tapeouts is a strong plus. Understanding of DFM is a plus. Calibre experience is a plus. - OR - DFT: The ideal candidate should be strong in all DFT (Design for Test) for all aspects. This would include - scan/TDF, TestKompress, MEMBIST/BISR, JTAG and etc. Having STA skills is a plus for all aspects of test. Responsible for support / debug of customer designs after delivery of prototypes

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