amd 上海招聘 asic design verification engineer

jj_seu

AMD 上海研发中心招聘 asic design verification engineer
msn:jj_seu@hotmail.com
qq: 1317656040
简历发 jane2.jin@amd.com
MTS/Sr. ASIC Engineer:
  
      
Position Summary
- Participate IP and SoC level architecture definition, derive functional and design specifications and analyze feasibility of technical and architectures.
- Implement design with verilog to achieve specification goals. Simulate and debug the codes in coding stage.
- Go through the FE design flow to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan.
- Write ASIC specific part of test plan. Prove functional correctness from block level to SoC level
- Support FW/SW bring-up and debugging
- Working as the technical point of contact on the ASIC area.
- Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.

Essential Functions:
RTL, Verification, Testbench, SystemC, SystemVerilog, OVM
Essential Requirements/Qualifications:
- Proven ASIC / SoC Design / Verification Experience
- Must have strong background on IP development

Desired:
- Major in EE & CS
- Must be proficient in Verilog coding, debugging and modeling
- Should be familiar with Advanced C/C++/SystemVerilog, RTL coding techniques.
- PCIe, BIOS, ACPI experience would be an asset.
- Must be familiar with Design for verification Methodology (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
- Should be familiar with ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc.
- Must be familiar with shell/perl/tcl programming in linux OS.
- Should have strong problem solving skills
- Good English hearing, speaking, reading and writing capabilities.
- Good communication skills
- Will be a big plus if having mass production tape‐out experience.

iseesky

要求不低。

美丽芯灵

貌似 我符合这个要求